双口RAM
IP配置
激励文件
`timescale 1ns / 1ps
`define clk_period 20
module dpram_tb( );reg clock;reg [7:0]data;reg [7:0]rdaddress;reg [7:0]wraddress;reg wren;wire [7:0]q;integer i;dist_mem_gen_0 dist_mem_gen_0 (.a(data), // input wire [7 : 0] a.d(rdaddress), // input wire [7 : 0] d.dpra(wraddress), // input wire [7 : 0] dpra.clk(clock), // input wire clk.we(wren), // in
