PCI_Express规范第七章解读-Software Initialization and configuration

7.Software Initialization and configuration

PCI EXPRESS Configuration model 支持两种配置空间的访问机制：

-PCI 兼容配置机制：100%的二进制兼容PCI 2.3中定义的，以及兼容早期的OS或类似的总线枚举和配置软件。

-PCI Express增强配置机制：提供了更大有效的配置空间，以及更有效的访问机制。

7.1 Configuration Topology

-PCI Express Link：A Link represents a dual-simplex communications channel between two components。

-Root Complex: RC的主要功能与PCI总线中的HOST主桥类似，但是在HOST主桥的基础上增加了许多功能。

7.2 PCI Express Configuration Mechanisms

PCI Express 配置空间图：

-1.PCI Express把PCI SPEC 2.3中规定的配置空间从256byte扩展了至4096 byte。

-2.PCI Express configuration space分为两部分：

--1.PCI 2.3兼容部分，它包含每一个逻辑设备的配置空间的第一个256bytes。
--2.PCI Express扩展部分，包括剩下的区域。

-3.PCI 2.3兼容部分可以用任何一种在PCI 2.3中定义的访问机制访问，也可以用PCI EXPRESS定义的配置访问方式 访问（后面介绍）。

-4.PCI Express扩展空间部分只能用PCI Express configuration access mechanism。

对于PCI 2.3兼容部分的访问方式如下：

1.每一個PCI device都有其 unique PFA(PCI Function Address). PFA由 bus number,device number & function number所組成.例如. USB device PFA is (0,6,0) <- USB is a PCI device and its bus/dev/function is 0/6/0。

   -- 有了PFA,就可以存取其 PCI configuration registers.

Ex. write USB PCI register 43h bit1 = 1

mov eax, 80003040h
mov dx, 0cf8h
out dx, eax

mov dx, 0cffh
in al, dx
or al, 00000010b
out dx, al

对于.PCI Express扩展空间部分的访问：
Ex. mov ax, [50400000h] <- read device (4,0,0)'s register 0;2 bytesNote: PCIe extended base address 要 reserve and report to OS. Size is 256MByte. 這是BIOS需要做的. (當然,BIOS也要將此 base address寫入 chipset register,讓 chipset 知道:有這樣的 cycle時,是給PCIe device的 ! )-繁体字部分来自网络

here 50000000h: PCIe extended base address. 可以從 chipset register得知
     bit[27:20]: Bus information
     [19:15]: Device information
     [14:12]: Function information
     [11: 8]: Extended Register
     [7:2]: DW number
     [1:0]: Byte enable

因此,只要知道 PCIe extended base address,就可以像以前一樣,可以任意存取 PCIe config registers, 即可以访问 0FFh 。

NOTE:实际上，pcie device可以由其PCI 2.3兼容部分里的Capabilities Pointer Register识别，因为在眾多的 capabilities中,會有一個 PCIe capability;其 ID value = 10h.

ID	Description
00h	Reserved.
01h	PCI Power Management Interface. Refer to "The PM Capability Register Set" on page 585.
02h	AGP. Refer to "AGP Capability" on page 845. Also refer to the MindShare book entitled AGP System Architecture, Second Edition (published by Addison-Wesley).
03h	VPD. Refer to "Vital Product Data (VPD) Capability" on page 848.
04h	Slot Identification. This capability identifies a bridge that provides external expansion capabilities (i.e., an expansion chassis containing add-in card slots). Full documentation of this feature can be found in the revision 1.1 PCI-to-PCI Bridge Architecture Specification. For a detailed, Express-oriented description, refer to "Introduction To Chassis/Slot Numbering Registers" on page 859 and "Chassis and Slot Number Assignment" on page 861.
05h	Message Signaled Interrupts. Refer to "The MSI Capability Register Set" on page 332.
06h	CompactPCI Hot Swap. Refer to the chapter entitled Compact PCI and PMC in the MindShare book entitled PCI System Architecture, Fourth Edition (published by Addison-Wesley).
07h	PCI-X device. For a detailed description, refer to the MindShare book entitled PCI-X System Architecture (published by Addison-Wesley).
08h	Reserved for AMD.
09h	Vendor Specific capability register set. The layout of the register set is vendor specific, except that the byte immediately following the "Next" pointer indicates the number of bytes in the capability structure (including the ID and Next pointer bytes). An example vendor specific usage is a function that is configured in the final manufacturing steps as either a 32-bit or 64-bit PCI agent and the Vendor Specific capability structure tells the device driver which features the device supports.
0Ah	Debug port.
0Bh	CompactPCI central resource control. A full definition of this capability can be found in the PICMG 2.13 Specification (http://www.picmg.com).
0Ch	PCI Hot-Plug. This ID indicates that the associated device conforms to the Standard Hot-Plug Controller model.
0Dh-0Fh	Reserved.
10h	PCI Express Capability register set (aka PCI Express Capability Structure). For a detailed explanation, refer to "PCI Express Capability Register Set" on page 896.
11h-FFh	Reserve

3.8.2.12 HECBASE - PCI Express Extended Configuration Base Address Register
This register defines the base address of the enhanced PCI Express configuration
memory.

Device: 16
Function: 0
Offset: 64h
Version: Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Bit        Attr      Default     Description
31:24 RV       0h              Reserved

23:12 RW      001h           HECBASE: PCI Express Extended Configuration Base This register   contains     the address that corresponds to bits 39 to 28 of the base address for PCI Express extended   configuration space. Configuration software will read this register to determine where the 256MB range of addresses resides for this particular host bridg e. This register defaults to the same address as the default value for TOLM.
11:0 RV                 0h    Reserved

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