时钟初始化函数内容如下：

/** system_clock_init: Initialize core clock and bus clock.* void system_clock_init(void)*/
system_clock_init:ldr	r0, =ELFIN_CLOCK_POWER_BASE	@0xe0100000/* Set Mux to FIN */ldr	r1, =0x0str	r1, [r0, #CLK_SRC0_OFFSET]ldr	r1,	=APLL_LOCKTIME_VALstr	r1,	[r0, #APLL_LOCK_OFFSET]/********lxg added*********************/ldr	r0, =ELFIN_CLOCK_POWER_BASE	@0xe0100000ldr	r1,	=MPLL_LOCKTIME_VALstr	r1,	[r0, #MPLL_LOCK_OFFSET]/********end*********************//* Disable PLL */
#if defined(CONFIG_CHECK_MPLL_LOCK)
retryloop:
#endifldr	r1, =0x0str	r1, [r0, #APLL_CON0_OFFSET]ldr	r1, =0x0str	r1, [r0, #MPLL_CON_OFFSET]ldr	r1, =0x0str	r1, [r0, #MPLL_CON_OFFSET]ldr   	r1, [r0, #CLK_DIV0_OFFSET]ldr	r2, =CLK_DIV0_MASKbic	r1, r1, r2ldr	r2, =CLK_DIV0_VALorr	r1, r1, r2str	r1, [r0, #CLK_DIV0_OFFSET]ldr	r1, =APLL_VALstr	r1, [r0, #APLL_CON0_OFFSET]ldr	r1, =MPLL_VALstr	r1, [r0, #MPLL_CON_OFFSET]ldr	r1, =VPLL_VALstr	r1, [r0, #VPLL_CON_OFFSET]/*******lxg added***********************/ldr	r1, =EPLL_VALstr	r1, [r0, #EPLL_CON_OFFSET]/*******lxg added***********************/ldr   	r1, [r0, #CLK_DIV1_OFFSET]ldr	r2, =CLK_DIV1_MASKbic	r1, r1, r2ldr	r2, =CLK_DIV1_VALorr	r1, r1, r2str	r1, [r0, #CLK_DIV1_OFFSET]ldr   	r1, [r0, #CLK_DIV2_OFFSET]ldr	r2, =CLK_DIV2_MASKbic	r1, r1, r2ldr	r2, =CLK_DIV2_VALorr	r1, r1, r2str	r1, [r0, #CLK_DIV2_OFFSET]ldr   	r1, [r0, #CLK_DIV4_OFFSET]ldr	r2, =CLK_DIV4_MASKbic	r1, r1, r2ldr	r2, =CLK_DIV4_VALorr	r1, r1, r2str	r1, [r0, #CLK_DIV4_OFFSET]ldr   	r1, [r0, #CLK_DIV6_OFFSET]ldr	r2, =CLK_DIV6_MASKbic	r1, r1, r2ldr	r2, =CLK_DIV6_VALorr	r1, r1, r2str	r1, [r0, #CLK_DIV6_OFFSET]/*******end*****************//*******end*****************/
#if defined(CONFIG_EVT1)ldr	r1, =AFC_ONstr	r1, [r0, #APLL_CON1_OFFSET]
#endifmov	r1, #0x10000
1:	subs	r1, r1, #1bne	1b#if defined(CONFIG_CHECK_MPLL_LOCK)/* MPLL software workaround */ldr	r1, [r0, #MPLL_CON_OFFSET]orr     r1, r1, #(1<<28)str	r1, [r0, #MPLL_CON_OFFSET]mov	r1, #0x100
1:	subs	r1, r1, #1bne	1bldr	r1, [r0, #MPLL_CON_OFFSET]and	r1, r1, #(1<<29)cmp	r1, #(1<<29)bne 	retryloop/* H/W lock detect disable */ldr	r1, [r0, #MPLL_CON_OFFSET]bic     r1, r1, #(1<<28)str	r1, [r0, #MPLL_CON_OFFSET]
#endifldr	r1, [r0, #CLK_SRC0_OFFSET]//ldr	r2, =0x10001111 //lxg changed.ldr	r2, =0x00000111orr	r1, r1, r2str	r1, [r0, #CLK_SRC0_OFFSET]// added by terry 2012.12.4 for camera ldr r1, [r0, #CLK_SRC1_OFFSET]bic r1, r1, #(0xf<<12)orr r1, r1, #(0x1<<12) //0001 XusbXTIstr r1, [r0, #CLK_SRC1_OFFSET]#if defined(CONFIG_MCP_AC)/* CLK_SRC6[25:24] -> OneDRAM clock sel = MPLL */ldr	r1, [r0, #CLK_SRC6_OFFSET]bic	r1, r1, #(0x3<<24)orr	r1, r1, #0x01000000str	r1, [r0, #CLK_SRC6_OFFSET]/* CLK_DIV6[31:28] -> 4=1/5, 3=1/4(166MHZ@667MHz), 2=1/3 */ldr	r1, [r0, #CLK_DIV6_OFFSET]bic	r1, r1, #(0xF<<28)bic	r1, r1, #(0x7<<12)	@; ONENAND_RATIO: 0orr	r1, r1, #0x30000000str	r1, [r0, #CLK_DIV6_OFFSET]#elif defined (CONFIG_MCP_H)/* CLK_SRC6[25:24] -> OneDRAM clock sel = 00:SCLKA2M, 01:SCLKMPLL */ldr	r1, [r0, #CLK_SRC6_OFFSET]bic	r1, r1, #(0x3<<24)orr	r1, r1, #0x00000000str	r1, [r0, #CLK_SRC6_OFFSET]/* CLK_DIV6[31:28] -> 4=1/5, 3=1/4(166MHZ@667MHz), 2=1/3 */ldr	r1, [r0, #CLK_DIV6_OFFSET]bic	r1, r1, #(0xF<<28)bic	r1, r1, #(0x7<<12)	@; ONENAND_RATIO: 0orr	r1, r1, #0x00000000str	r1, [r0, #CLK_DIV6_OFFSET]	#elif defined (CONFIG_MCP_B) || defined (CONFIG_MCP_D)/* CLK_SRC6[25:24] -> OneDRAM clock sel = 00:SCLKA2M, 01:SCLKMPLL */ldr	r1, [r0, #CLK_SRC6_OFFSET]bic	r1, r1, #(0x3<<24)orr	r1, r1, #0x01000000str	r1, [r0, #CLK_SRC6_OFFSET]/* CLK_DIV6[31:28] -> 4=1/5, 3=1/4(166MHZ@667MHz), 2=1/3 */ldr	r1, [r0, #CLK_DIV6_OFFSET]bic	r1, r1, #(0xF<<28)bic	r1, r1, #(0x7<<12)	@; ONENAND_RATIO: 0orr	r1, r1, #0x30000000str	r1, [r0, #CLK_DIV6_OFFSET]#elif defined (CONFIG_MCP_SINGLE)/* CLK_DIV6 *//*ldr	r1, [r0, #CLK_DIV6_OFFSET]bic	r1, r1, #(0x7<<12)	@; ONENAND_RATIO: 0str	r1, [r0, #CLK_DIV6_OFFSET]*/ //lxg mask#endif	mov	pc, lr