![verilog HDLBits刷题[Building Larger Circuits]“Exams/review2015 fsmseq”---FSM :Sequence 1101 recognizer](http://pic.xiahunao.cn/yaotu/verilog HDLBits刷题[Building Larger Circuits]“Exams/review2015 fsmseq”---FSM :Sequence 1101 recognizer)
1、题目This is the second component in a series of five exercises that builds a complex counter out of several smaller circuits. See the final exercise for the overall design.Build a finite-state machine that searches for the sequence 1101 in an input bit stream. When the sequence is found, it should set start_shifting to 1, forever, until reset. Getting stuck in the final state is intended to model going to other states in a bigger FSM that is not yet implemented. We will be extending this FSM in the next few exercises.2、分析构建状态机寻找序列1101找到后将start_shifting永久置1直到复位的出现才变为0该序列有4bit如果加上IDEL一共5个状态到第5个状态后也就是已经找到1101后不管输入是什么输出一直保持1第五个状态后就保持第五个状态3、代码module top_module ( input clk, input reset, // Synchronous reset input data, output start_shifting); parameter IDEL3d0,BIT13d1,BIT23d2,BIT33d3,BIT43d4; reg [2:0]state,next_state; always(posedge clk)begin if(reset) stateIDEL; else statenext_state; end always(*)begin case(state) IDEL:next_statedata?BIT1:IDEL; BIT1:next_statedata?BIT2:IDEL; BIT2:next_statedata?BIT2:BIT3; BIT3:next_statedata?BIT4:IDEL; BIT4:next_stateBIT4; default:next_stateIDEL; endcase end assign start_shifting(stateBIT4); endmodule4、结果 verilog HDLBits刷题[Building Larger Circuits]“Exams/review2015 fsmseq”---FSM :Sequence 1101 recognizer
1、题目This is the second component in a series of five exercises that builds a complex counter out of several smaller circuits. See the final exercise for the overall design.Build a finite-state machine that searches for the sequence 1101 in an input bit stream. When the sequence is found, it should set start_shifting to 1, forever, until reset. Getting stuck in the final state is intended to model going to other states in a bigger FSM that is not yet implemented. We will be extending this FSM in the next few exercises.2、分析构建状态机寻找序列1101找到后将start_shifting永久置1直到复位的出现才变为0该序列有4bit如果加上IDEL一共5个状态到第5个状态后也就是已经找到1101后不管输入是什么输出一直保持1第五个状态后就保持第五个状态3、代码module top_module ( input clk, input reset, // Synchronous reset input data, output start_shifting); parameter IDEL3d0,BIT13d1,BIT23d2,BIT33d3,BIT43d4; reg [2:0]state,next_state; always(posedge clk)begin if(reset) stateIDEL; else statenext_state; end always(*)begin case(state) IDEL:next_statedata?BIT1:IDEL; BIT1:next_statedata?BIT2:IDEL; BIT2:next_statedata?BIT2:BIT3; BIT3:next_statedata?BIT4:IDEL; BIT4:next_stateBIT4; default:next_stateIDEL; endcase end assign start_shifting(stateBIT4); endmodule4、结果