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网站建设攵金手指科杰壹陆,互联网产品代理项目,公司做网站怎么赚钱,做商品条形码的网站本文主要探讨210的LCD相关知识。 LCD LCD称液晶(透光背光呈色),可在电信号驱动下使液晶分子旋转,呈现不同的颜色(被动发光) lcd接口为TTL接口(5V为1#xff0c;0V为0),不能传输太远,远距离传输方式:SoC(TTL) -VGA- LCD(TTL) 其他显设备:CRT(…        本文主要探讨210的LCD相关知识。 LCD         LCD称液晶(透光背光呈色),可在电信号驱动下使液晶分子旋转,呈现不同的颜色(被动发光)         lcd接口为TTL接口(5V为10V为0),不能传输太远,远距离传输方式:SoC(TTL) -VGA- LCD(TTL)         其他显设备:CRT(阴极摄像管显示器),OLED,LED         RGB接口:VD0~23 24根数据线,HSYNC水平同步信号,VSYNC垂直同步信号,VCLK像素时钟,VDEN数据有效标志,LEND行结束标志 lcd显示         像素是组成图像的最基本元素(最小单位),扫描频率为刷新率         LCD显示单位为帧(一画面),一帧为多行,一行为多像素(像素矩阵)         LCD控制器通过数字接口给LCD驱动器提供数字信号         LCD驱动器给面板提供模拟电信号         显存是LCD控制器读取像素数据传输给LCD驱动器的区域         像素间距pitch是连续2个像素中心距离         分辨率resolution:屏幕的横纵像素个数就叫分辨率(210是800×480) 像素深度bpp:计算机用二进制位来表示像素的数据,位越多像素颜色值越多(1、8、16、24、32位)         24位24二进制位表示颜色可表示16777216种颜色(RGB888分布)         210LCD控制器叫FIMD与AHB总线连接,对外部提供RGB接口、I80接口、YUV接口         210LCD控制器有5个虚拟屏幕Window0~Window4         HSPW水平同步信号脉宽         HBPD水平同步信号前肩         HFPD水平同步信号后肩         VSPW垂直同步信号脉宽         VBPD垂直同步信号前肩         VFPD垂直同步信号后肩         一行像素数据显示(LCD兼容):LCD控制器发送HSYNC高电平脉冲宽度为HSPW,HBPD有效行信息HFPD(三部分)或HSPWHBPD有效行信息HFPD(四部分)         一帧帧图像显示(LCD兼容)VSPW(帧同步信号宽度)VBPD帧有效信号VFPD         210的LCD时序参数             h_fp     210                     h_bp     38                      h_sw     10                  v_fp     22                 v_fpe     1             v_bp     18                  v_bpe     1                 v_sw     7         210lcd寄存器 gpio GPF0CON~GPF3CON(配置lcd功能) GPD0CONGPD0DAT配置背光 lcd寄存器 DISPLAY_CONTROL设置rgb模式10或11 VIDCON0~VIDCON3配置LCD主控制 VIDTCON0~VIDTCON3设置时序 VINCON0~VINCON4设置window 设置发送数据的通道 设置坐标和范围 设置window0 起始地址和缓存 demo:        画线,画圆,写英文,显示图片 Makefile(主) all:make -C ./bl1 make -C ./bl2 clean:make clean -C ./bl1make clean -C ./bl2 writersd #!/bin/sh dd iflagdsync oflagdsync if./bl1/sd1.bin of/dev/sdb seek1 dd iflagdsync oflagdsync if./bl2/sd2.bin of/dev/sdb seek45 bl1: start.S #define WTCON 0xE2700000 #define SVC_STACK 0xd0037d80 #define SOFT_SW 0xE010E81C.global _start_start://set soft switcher,mean set XEINT[0] as PS_HOLD_OUT_EN,set output high levelldr r0, SOFT_SWldr r1, [r0]orr r1, r1, #0x300orr r1, r1, #0x01str r1, [r0]//close WatchDogldr r0,WTCONldr r1,0x0str r1,[r0]//init SVC stackldr sp,SVC_STACK//init icachemrc p15,0,r0,c1,c0,0bic r0,r0,#(112) //close icacheorr r0,r0,#(112) //open icachemcr p15,0,r0,c1,c0,0 bl sdram_asm_init//use funcbl copy_bl2_2_ddrb . s5pv210.h /* S5PC110 device base addresses */ #define ELFIN_DMA_BASE 0xE0900000 #define ELFIN_LCD_BASE 0xF8000000 #define ELFIN_USB_HOST_BASE 0xEC200000 #define ELFIN_I2C_BASE 0xE1800000 #define ELFIN_I2S_BASE 0xE2100000 #define ELFIN_ADC_BASE 0xE1700000 #define ELFIN_SPI_BASE 0xE1300000#define ELFIN_HSMMC_0_BASE 0xEB000000 #define ELFIN_HSMMC_1_BASE 0xEB100000 #define ELFIN_HSMMC_2_BASE 0xEB200000 #define ELFIN_HSMMC_3_BASE 0xEB300000#define ELFIN_CLOCK_POWER_BASE 0xE0100000#define IO_RET_REL ((1 31) | (1 29) | (1 28))/* Clock Power Controller for s5pc110*/ #define APLL_LOCK_OFFSET 0x00 #define MPLL_LOCK_OFFSET 0x08 #define EPLL_LOCK_OFFSET 0x10 #define VPLL_LOCK_OFFSET 0x20 #define APLL_CON0_OFFSET 0x100 #define APLL_CON1_OFFSET 0x104 #define MPLL_CON_OFFSET 0x108 #define EPLL_CON_OFFSET 0x110 #define VPLL_CON_OFFSET 0x120#define CLK_SRC0_OFFSET 0x200 #define CLK_SRC1_OFFSET 0x204 #define CLK_SRC2_OFFSET 0x208 #define CLK_SRC3_OFFSET 0x20c #define CLK_SRC4_OFFSET 0x210 #define CLK_SRC5_OFFSET 0x214 #define CLK_SRC6_OFFSET 0x218 #define CLK_SRC_MASK0_OFFSET 0x280 #define CLK_SRC_MASK1_OFFSET 0x284#define CLK_DIV0_OFFSET 0x300 #define CLK_DIV1_OFFSET 0x304 #define CLK_DIV2_OFFSET 0x308 #define CLK_DIV3_OFFSET 0x30c #define CLK_DIV4_OFFSET 0x310 #define CLK_DIV5_OFFSET 0x314 #define CLK_DIV6_OFFSET 0x318 #define CLK_DIV7_OFFSET 0x31c#define CLK_GATE_IP0_OFFSET 0x460 #define CLK_GATE_IP1_OFFSET 0x464 #define CLK_GATE_IP2_OFFSET 0x468 #define CLK_GATE_IP3_OFFSET 0x46c #define CLK_GATE_IP4_OFFSET 0x470 #define CLK_GATE_BLOCK_OFFSET 0x480#define CLK_OUT_OFFSET 0x500 #define CLK_DIV_STAT0_OFFSET 0x1000 #define CLK_DIV_STAT1_OFFSET 0x1004 #define CLK_MUX_STAT0_OFFSET 0x1100 #define CLK_MUX_STAT1_OFFSET 0x1104 #define SW_RST_OFFSET 0x2000#define ONEDRAM_CFG_OFFSET 0x6208#define OSC_CON_OFFSET 0x8000 #define RST_STAT_OFFSET 0xa000 #define PWR_CFG_OFFSET 0xc000 #define EINT_WAKEUP_MASK_OFFSET 0xc004 #define WAKEUP_MASK_OFFSET 0xc008 #define NORMAL_CFG_OFFSET 0xc010 #define IDLE_CFG_OFFSET 0xc020 #define STOP_CFG_OFFSET 0xc030 #define STOP_MEM_CFG_OFFSET 0xc034 #define SLEEP_CFG_OFFSET 0xc040 #define OSC_FREQ_OFFSET 0xc100 #define OSC_STABLE_OFFSET 0xc104 #define PWR_STABLE_OFFSET 0xc108 #define MTC_STABLE_OFFSET 0xc110 #define CLAMP_STABLE_OFFSET 0xc114 #define WAKEUP_STAT_OFFSET 0xc200 #define BLK_PWR_STAT_OFFSET 0xc204 #define BODY_BIAS_CON_OFFSET 0xc300 #define ION_SKEW_CON_OFFSET 0xc310 #define ION_SKEW_MON_OFFSET 0xc314 #define IOFF_SKEW_CON_OFFSET 0xc320 #define IOFF_SKEW_MON_OFFSET 0xc324 #define OTHERS_OFFSET 0xe000 #define OM_STAT_OFFSET 0xe100 #define MIE_CONTROL_OFFSET 0xe800 #define HDMI_CONTROL_OFFSET 0xe804 #define USB_PHY_CONTROL_OFFSET 0xe80c #define DAC_CONTROL_OFFSET 0xe810 #define MIPI_DPHY_CONTROL_OFFSET 0xe814 #define ADC_CONTROL_OFFSET 0xe818 #define PS_HOLD_CONTROL_OFFSET 0xe81c#define INFORM0_OFFSET 0xf000 #define INFORM1_OFFSET 0xf004 #define INFORM2_OFFSET 0xf008 #define INFORM3_OFFSET 0xf00c #define INFORM4_OFFSET 0xf010 #define INFORM5_OFFSET 0xf014 #define INFORM6_OFFSET 0xf018 #define INFORM7_OFFSET 0xf01c#define INF_REG0_OFFSET 0x00 #define INF_REG1_OFFSET 0x04 #define INF_REG2_OFFSET 0x08 #define INF_REG3_OFFSET 0x0c #define INF_REG4_OFFSET 0x10 #define INF_REG5_OFFSET 0x14 #define INF_REG6_OFFSET 0x18 #define INF_REG7_OFFSET 0x1c/** GPIO*/ #define ELFIN_GPIO_BASE 0xE0200000#define GPA0CON_OFFSET 0x000 #define GPA0DAT_OFFSET 0x004 #define GPA0PUD_OFFSET 0x008 #define GPA0DRV_SR_OFFSET 0x00C #define GPA0CONPDN_OFFSET 0x010 #define GPA0PUDPDN_OFFSET 0x014#define GPA1CON_OFFSET 0x020 #define GPA1DAT_OFFSET 0x024 #define GPA1PUD_OFFSET 0x028 #define GPA1DRV_SR_OFFSET 0x02C #define GPA1CONPDN_OFFSET 0x030 #define GPA1PUDPDN_OFFSET 0x034#define GPBCON_OFFSET 0x040 #define GPBDAT_OFFSET 0x044 #define GPBPUD_OFFSET 0x048 #define GPBDRV_SR_OFFSET 0x04C #define GPBCONPDN_OFFSET 0x050 #define GPBPUDPDN_OFFSET 0x054#define GPC0CON_OFFSET 0x060 #define GPC0DAT_OFFSET 0x064 #define GPC0PUD_OFFSET 0x068 #define GPC0DRV_SR_OFFSET 0x06C #define GPC0CONPDN_OFFSET 0x070 #define GPC0PUDPDN_OFFSET 0x074#define GPC1CON_OFFSET 0x080 #define GPC1DAT_OFFSET 0x084 #define GPC1PUD_OFFSET 0x088 #define GPC1DRV_SR_OFFSET 0x08C #define GPC1CONPDN_OFFSET 0x090 #define GPC1PUDPDN_OFFSET 0x094#define GPD0CON_OFFSET 0x0A0 #define GPD0DAT_OFFSET 0x0A4 #define GPD0PUD_OFFSET 0x0A8 #define GPD0DRV_SR_OFFSET 0x0AC #define GPD0CONPDN_OFFSET 0x0B0 #define GPD0PUDPDN_OFFSET 0x0B4#define GPD1CON_OFFSET 0x0C0 #define GPD1DAT_OFFSET 0x0C4 #define GPD1PUD_OFFSET 0x0C8 #define GPD1DRV_SR_OFFSET 0x0CC #define GPD1CONPDN_OFFSET 0x0D0 #define GPD1PUDPDN_OFFSET 0x0D4#define GPE0CON_OFFSET 0x0E0 #define GPE0DAT_OFFSET 0x0E4 #define GPE0PUD_OFFSET 0x0E8 #define GPE0DRV_SR_OFFSET 0x0EC #define GPE0CONPDN_OFFSET 0x0F0 #define GPE0PUDPDN_OFFSET 0x0F4#define GPE1CON_OFFSET 0x100 #define GPE1DAT_OFFSET 0x104 #define GPE1PUD_OFFSET 0x108 #define GPE1DRV_SR_OFFSET 0x10C #define GPE1CONPDN_OFFSET 0x110 #define GPE1PUDPDN_OFFSET 0x114#define GPF0CON_OFFSET 0x120 #define GPF0DAT_OFFSET 0x124 #define GPF0PUD_OFFSET 0x128 #define GPF0DRV_SR_OFFSET 0x12C #define GPF0CONPDN_OFFSET 0x130 #define GPF0PUDPDN_OFFSET 0x134#define GPF1CON_OFFSET 0x140 #define GPF1DAT_OFFSET 0x144 #define GPF1PUD_OFFSET 0x148 #define GPF1DRV_SR_OFFSET 0x14C #define GPF1CONPDN_OFFSET 0x150 #define GPF1PUDPDN_OFFSET 0x154#define GPF2CON_OFFSET 0x160 #define GPF2DAT_OFFSET 0x164 #define GPF2PUD_OFFSET 0x168 #define GPF2DRV_SR_OFFSET 0x16C #define GPF2CONPDN_OFFSET 0x170 #define GPF2PUDPDN_OFFSET 0x174#define GPF3CON_OFFSET 0x180 #define GPF3DAT_OFFSET 0x184 #define GPF3PUD_OFFSET 0x188 #define GPF3DRV_SR_OFFSET 0x18C #define GPF3CONPDN_OFFSET 0x190 #define GPF3PUDPDN_OFFSET 0x194#define GPG0CON_OFFSET 0x1A0 #define GPG0DAT_OFFSET 0x1A4 #define GPG0PUD_OFFSET 0x1A8 #define GPG0DRV_SR_OFFSET 0x1AC #define GPG0CONPDN_OFFSET 0x1B0 #define GPG0PUDPDN_OFFSET 0x1B4#define GPG1CON_OFFSET 0x1C0 #define GPG1DAT_OFFSET 0x1C4 #define GPG1PUD_OFFSET 0x1C8 #define GPG1DRV_SR_OFFSET 0x1CC #define GPG1CONPDN_OFFSET 0x1D0 #define GPG1PUDPDN_OFFSET 0x1D4#define GPG2CON_OFFSET 0x1E0 #define GPG2DAT_OFFSET 0x1E4 #define GPG2PUD_OFFSET 0x1E8 #define GPG2DRV_SR_OFFSET 0x1EC #define GPG2CONPDN_OFFSET 0x1F0 #define GPG2PUDPDN_OFFSET 0x1F4#define GPG3CON_OFFSET 0x200 #define GPG3DAT_OFFSET 0x204 #define GPG3PUD_OFFSET 0x208 #define GPG3DRV_SR_OFFSET 0x20C #define GPG3CONPDN_OFFSET 0x210 #define GPG3PUDPDN_OFFSET 0x214#define MP1_0DRV_SR_OFFSET 0x3CC #define MP1_1DRV_SR_OFFSET 0x3EC #define MP1_2DRV_SR_OFFSET 0x40C #define MP1_3DRV_SR_OFFSET 0x42C #define MP1_4DRV_SR_OFFSET 0x44C #define MP1_5DRV_SR_OFFSET 0x46C #define MP1_6DRV_SR_OFFSET 0x48C #define MP1_7DRV_SR_OFFSET 0x4AC #define MP1_8DRV_SR_OFFSET 0x4CC#define MP2_0DRV_SR_OFFSET 0x4EC #define MP2_1DRV_SR_OFFSET 0x50C #define MP2_2DRV_SR_OFFSET 0x52C #define MP2_3DRV_SR_OFFSET 0x54C #define MP2_4DRV_SR_OFFSET 0x56C #define MP2_5DRV_SR_OFFSET 0x58C #define MP2_6DRV_SR_OFFSET 0x5AC #define MP2_7DRV_SR_OFFSET 0x5CC #define MP2_8DRV_SR_OFFSET 0x5EC/* GPH0 */ #define GPH0CON_OFFSET 0xc00 #define GPH0DAT_OFFSET 0xc04 #define GPH0PUD_OFFSET 0xc08 #define GPH0DRV_OFFSET 0xc0c/* GPH1 */ #define GPH1CON_OFFSET 0xc20 #define GPH1DAT_OFFSET 0xc24 #define GPH1PUD_OFFSET 0xc28 #define GPH1DRV_OFFSET 0xc2c/* GPH2 */ #define GPH2CON_OFFSET 0xc40 #define GPH2DAT_OFFSET 0xc44 #define GPH2PUD_OFFSET 0xc48 #define GPH2DRV_OFFSET 0xc4c/* GPH3 */ #define GPH3CON_OFFSET 0xc60 #define GPH3DAT_OFFSET 0xc64 #define GPH3PUD_OFFSET 0xc68 #define GPH3DRV_OFFSET 0xc6c#define GPICON_OFFSET 0x220 #define GPIPUD_OFFSET 0x228 #define GPIDRV_OFFSET_SR 0x22C #define GPIPUDPDN_OFFSET 0x234#define GPJ0CON_OFFSET 0x240 #define GPJ0DAT_OFFSET 0x244 #define GPJ0PUD_OFFSET 0x248 #define GPJ0DRV_SR_OFFSET 0x24C #define GPJ0CONPDN_OFFSET 0x250 #define GPJ0PUDPDN_OFFSET 0x254#define GPJ1CON_OFFSET 0x260 #define GPJ1DAT_OFFSET 0x264 #define GPJ1PUD_OFFSET 0x268 #define GPJ1DRV_SR_OFFSET 0x26C #define GPJ1CONPDN_OFFSET 0x270 #define GPJ1PUDPDN_OFFSET 0x274#define GPJ2CON_OFFSET 0x280 #define GPJ2DAT_OFFSET 0x284 #define GPJ2PUD_OFFSET 0x288 #define GPJ2DRV_SR_OFFSET 0x28C #define GPJ2CONPDN_OFFSET 0x290 #define GPJ2PUDPDN_OFFSET 0x294#define GPJ3CON_OFFSET 0x2A0 #define GPJ3DAT_OFFSET 0x2A4 #define GPJ3PUD_OFFSET 0x2A8 #define GPJ3DRV_SR_OFFSET 0x2AC #define GPJ3CONPDN_OFFSET 0x2B0 #define GPJ3PUDPDN_OFFSET 0x2B4#define GPJ4CON_OFFSET 0x2C0 #define GPJ4DAT_OFFSET 0x2C4 #define GPJ4PUD_OFFSET 0x2C8 #define GPJ4DRV_SR_OFFSET 0x2CC #define GPJ4CONPDN_OFFSET 0x2D0 #define GPJ4PUDPDN_OFFSET 0x2D4/** Interrupt*/ #define ELFIN_VIC0_BASE_ADDR (0xF2000000) #define ELFIN_VIC1_BASE_ADDR (0xF2100000) #define ELFIN_VIC2_BASE_ADDR (0xF2200000)#define ELFIN_TZIC0_BASE_ADDR (0xF2800000) #define ELFIN_TZIC1_BASE_ADDR (0xF2900000) #define ELFIN_TZIC2_BASE_ADDR (0xF2A00000)#define oINTMOD (0x0C) // VIC INT SELECT (IRQ or FIQ) #define oINTUNMSK (0x10) // VIC INT EN (Unmask by writing 1) #define oINTMSK (0x14) // VIC INT EN CLEAR (Mask by writing 1) #define oINTSUBMSK (0x1C) // VIC SOFT INT CLEAR #define oVECTADDR (0xF00) // VIC ADDRESS/** Watchdog timer*/ #define ELFIN_WATCHDOG_BASE 0xE2700000#define WTCON_OFFSET 0x00 #define WTDAT_OFFSET 0x08 #define WTCNT_OFFSET 0x0C#define WTCON_REG __REG(ELFIN_WATCHDOG_BASEWTCON_OFFSET) #define WTDAT_REG __REG(ELFIN_WATCHDOG_BASEWTDAT_OFFSET) #define WTCNT_REG __REG(ELFIN_WATCHDOG_BASEWTCNT_OFFSET)/** UART*/ #define ELFIN_UART_BASE 0XE2900000#define ELFIN_UART0_OFFSET 0x0000 #define ELFIN_UART1_OFFSET 0x0400 #define ELFIN_UART2_OFFSET 0x0800 #define ELFIN_UART3_OFFSET 0x0c00#if defined(CONFIG_SERIAL0) #define ELFIN_UART_CONSOLE_BASE (ELFIN_UART_BASE ELFIN_UART0_OFFSET) #elif defined(CONFIG_SERIAL1) #define ELFIN_UART_CONSOLE_BASE (ELFIN_UART_BASE ELFIN_UART1_OFFSET) #elif defined(CONFIG_SERIAL2) #define ELFIN_UART_CONSOLE_BASE (ELFIN_UART_BASE ELFIN_UART2_OFFSET) #elif defined(CONFIG_SERIAL3) #define ELFIN_UART_CONSOLE_BASE (ELFIN_UART_BASE ELFIN_UART3_OFFSET) #else #define ELFIN_UART_CONSOLE_BASE (ELFIN_UART_BASE ELFIN_UART0_OFFSET) #endif#define ULCON_OFFSET 0x00 #define UCON_OFFSET 0x04 #define UFCON_OFFSET 0x08 #define UMCON_OFFSET 0x0C #define UTRSTAT_OFFSET 0x10 #define UERSTAT_OFFSET 0x14 #define UFSTAT_OFFSET 0x18 #define UMSTAT_OFFSET 0x1C #define UTXH_OFFSET 0x20 #define URXH_OFFSET 0x24 #define UBRDIV_OFFSET 0x28 #define UDIVSLOT_OFFSET 0x2C #define UINTP_OFFSET 0x30 #define UINTSP_OFFSET 0x34 #define UINTM_OFFSET 0x38#define UTRSTAT_TX_EMPTY BIT2 #define UTRSTAT_RX_READY BIT0 #define UART_ERR_MASK 0xF/** PWM timer*/ #define ELFIN_TIMER_BASE 0xE2500000#define TCFG0_REG __REG(0xE2500000) #define TCFG1_REG __REG(0xE2500004) #define TCON_REG __REG(0xE2500008) #define TCNTB0_REG __REG(0xE250000c) #define TCMPB0_REG __REG(0xE2500010) #define TCNTO0_REG __REG(0xE2500014) #define TCNTB1_REG __REG(0xE2500018) #define TCMPB1_REG __REG(0xE250001c) #define TCNTO1_REG __REG(0xE2500020) #define TCNTB2_REG __REG(0xE2500024) #define TCMPB2_REG __REG(0xE2500028) #define TCNTO2_REG __REG(0xE250002c) #define TCNTB3_REG __REG(0xE2500030) #define TCMPB3_REG __REG(0xE2500034) #define TCNTO3_REG __REG(0xE2500038) #define TCNTB4_REG __REG(0xE250003c) #define TCNTO4_REG __REG(0xE2500040) #define TINT_CSTAT __REG(0xE2500044)/* Fields */ #define fTCFG0_DZONE Fld(8,16) /* the dead zone length ( timer 0) */ #define fTCFG0_PRE1 Fld(8,8) /* prescaler value for time 2,3,4 */ #define fTCFG0_PRE0 Fld(8,0) /* prescaler value for time 0,1 */ #define fTCFG1_MUX4 Fld(4,16) /* bits */ #define TCFG0_DZONE(x) FInsrt((x), fTCFG0_DZONE) #define TCFG0_PRE1(x) FInsrt((x), fTCFG0_PRE1) #define TCFG0_PRE0(x) FInsrt((x), fTCFG0_PRE0) #define TCON_4_AUTO (1 22) /* auto reload on/off for Timer 4 */ #define TCON_4_UPDATE (1 21) /* manual Update TCNTB4 */ #define TCON_4_ONOFF (1 20) /* 0: Stop, 1: start Timer 4 */ #define COUNT_4_ON (TCON_4_ONOFF*1) #define COUNT_4_OFF (TCON_4_ONOFF*0) #define TCON_3_AUTO (1 19) /* auto reload on/off for Timer 3 */ #define TIMER3_ATLOAD_ON (TCON_3_AUTO*1) #define TIMER3_ATLAOD_OFF FClrBit(TCON, TCON_3_AUTO) #define TCON_3_INVERT (1 18) /* 1: Inverter on for TOUT3 */ #define TIMER3_IVT_ON (TCON_3_INVERT*1) #define TIMER3_IVT_OFF (FClrBit(TCON, TCON_3_INVERT)) #define TCON_3_MAN (1 17) /* manual Update TCNTB3,TCMPB3 */ #define TIMER3_MANUP (TCON_3_MAN*1) #define TIMER3_NOP (FClrBit(TCON, TCON_3_MAN)) #define TCON_3_ONOFF (1 16) /* 0: Stop, 1: start Timer 3 */ #define TIMER3_ON (TCON_3_ONOFF*1) #define TIMER3_OFF (FClrBit(TCON, TCON_3_ONOFF)) /* macros */ #define GET_PRESCALE_TIMER4(x) FExtr((x), fTCFG0_PRE1) #define GET_DIVIDER_TIMER4(x) FExtr((x), fTCFG1_MUX4)#define MP01CON_OFFSET 0x2E0 #define MP01DAT_OFFSET 0x2E4 #define MP01PUD_OFFSET 0x2E8 #define MP01DRV_SR_OFFSET 0x2EC #define MP01CONPDN_OFFSET 0x2E0 #define MP01PUDPDN_OFFSET 0x2E4#define MP02CON_OFFSET 0x300 #define MP02DAT_OFFSET 0x304 #define MP02PUD_OFFSET 0x308 #define MP02DRV_SR_OFFSET 0x30c #define MP02CONPDN_OFFSET 0x310 #define MP02PUDPDN_OFFSET 0x314#define MP03CON_OFFSET 0x320 #define MP03DAT_OFFSET 0x324 #define MP03PUD_OFFSET 0x328 #define MP03DRV_SR_OFFSET 0x32c #define MP03CONPDN_OFFSET 0x330 #define MP03PUDPDN_OFFSET 0x334#define MP06CON_OFFSET 0x380 #define MP06DAT_OFFSET 0x384 #define MP06PUD_OFFSET 0x388 #define MP06DRV_SR_OFFSET 0x38C #define MP06CONPDN_OFFSET 0x390 #define MP06PUDPDN_OFFSET 0x394#define MP07CON_OFFSET 0x3A0 #define MP07DAT_OFFSET 0x3A4 #define MP07PUD_OFFSET 0x3A8 #define MP07DRV_SR_OFFSET 0x3AC #define MP07CONPDN_OFFSET 0x3B0 #define MP07PUDPDN_OFFSET 0x3B4/** Nand flash controller*/ #define ELFIN_NAND_BASE 0xB0E00000 #define ELFIN_NAND_ECC_BASE 0xB0E20000#define NFCONF_OFFSET 0x00 #define NFCONT_OFFSET 0x04 #define NFCMMD_OFFSET 0x08 #define NFADDR_OFFSET 0x0c #define NFDATA_OFFSET 0x10 #define NFMECCDATA0_OFFSET 0x14 #define NFMECCDATA1_OFFSET 0x18 #define NFSECCDATA0_OFFSET 0x1c #define NFSBLK_OFFSET 0x20 #define NFEBLK_OFFSET 0x24 #define NFSTAT_OFFSET 0x28 #define NFESTAT0_OFFSET 0x2c #define NFESTAT1_OFFSET 0x30 #define NFMECC0_OFFSET 0x34 #define NFMECC1_OFFSET 0x38 #define NFSECC_OFFSET 0x3c #define NFMLCBITPT_OFFSET 0x40 #define NFECCCONF_OFFSET 0x000 // R/W ECC configuration register 0x0000_0000 #define NFECCCONT_OFFSET 0x020 // R/W ECC control register 0x0000_0000 #define NFECCSTAT_OFFSET 0x030 // R ECC status register 0x0000_0000 #define NFECCSECSTAT_OFFSET 0x040 // R ECC sector status register 0x0000_0000 #define NFECCPRGECC0_OFFSET 0x090 // R ECC parity code0 register for page program 0x0000_0000 #define NFECCPRGECC1_OFFSET 0x094 // R ECC parity code1 register for page program 0x0000_0000 #define NFECCPRGECC2_OFFSET 0x098 // R ECC parity code2 register for page program 0x0000_0000 #define NFECCPRGECC3_OFFSET 0x09C // R ECC parity code3 register for page program 0x0000_0000 #define NFECCPRGECC4_OFFSET 0x0A0 // R ECC parity code4 register for page program 0x0000_0000 #define NFECCPRGECC5_OFFSET 0x0A4 // R ECC parity code5 register for page program 0x0000_0000 #define NFECCPRGECC6_OFFSET 0x0A8 // R ECC parity code6 register for page program 0x0000_0000 #define NFECCERL0_OFFSET 0x0C0 // R ECC error byte location0 register 0x0000_0000 #define NFECCERL1_OFFSET 0x0C4 // R ECC error byte location1 register 0x0000_0000 #define NFECCERL2_OFFSET 0x0C8 // R ECC error byte location2 register 0x0000_0000 #define NFECCERL3_OFFSET 0x0CC // R ECC error byte location3 register 0x0000_0000 #define NFECCERL4_OFFSET 0x0D0 // R ECC error byte location4 register 0x0000_0000 #define NFECCERL5_OFFSET 0x0D4 // R ECC error byte location5 register 0x0000_0000 #define NFECCERL6_OFFSET 0x0D8 // R ECC error byte location6 register 0x0000_0000 #define NFECCERL7_OFFSET 0x0DC // R ECC error byte location7 register 0x0000_0000 #define NFECCERP0_OFFSET 0x0F0 // R ECC error bit pattern0 register 0x0000_0000 #define NFECCERP1_OFFSET 0x0F4 // R ECC error bit pattern1 register 0x0000_0000 #define NFECCERP2_OFFSET 0x0F8 // R ECC error bit pattern2 register 0x0000_0000 #define NFECCERP3_OFFSET 0x0FC // R ECC error bit pattern3 register 0x0000_0000 #define NFECCCONECC0_OFFSET 0x110 // R/W ECC parity conversion code0 register 0x0000_0000 #define NFECCCONECC1_OFFSET 0x114 // R/W ECC parity conversion code1 register 0x0000_0000 #define NFECCCONECC2_OFFSET 0x118 // R/W ECC parity conversion code2 register 0x0000_0000 #define NFECCCONECC3_OFFSET 0x11C // R/W ECC parity conversion code3 register 0x0000_0000 #define NFECCCONECC4_OFFSET 0x120 // R/W ECC parity conversion code4 register 0x0000_0000 #define NFECCCONECC5_OFFSET 0x124 // R/W ECC parity conversion code5 register 0x0000_0000 #define NFECCCONECC6_OFFSET 0x128 // R/W ECC parity conversion code6 register 0x0000_0000#define NFCONF (ELFIN_NAND_BASENFCONF_OFFSET) #define NFCONT (ELFIN_NAND_BASENFCONT_OFFSET) #define NFCMMD (ELFIN_NAND_BASENFCMMD_OFFSET) #define NFADDR (ELFIN_NAND_BASENFADDR_OFFSET) #define NFDATA (ELFIN_NAND_BASENFDATA_OFFSET) #define NFMECCDATA0 (ELFIN_NAND_BASENFMECCDATA0_OFFSET) #define NFMECCDATA1 (ELFIN_NAND_BASENFMECCDATA1_OFFSET) #define NFSECCDATA0 (ELFIN_NAND_BASENFSECCDATA0_OFFSET) #define NFSBLK (ELFIN_NAND_BASENFSBLK_OFFSET) #define NFEBLK (ELFIN_NAND_BASENFEBLK_OFFSET) #define NFSTAT (ELFIN_NAND_BASENFSTAT_OFFSET) #define NFESTAT0 (ELFIN_NAND_BASENFESTAT0_OFFSET) #define NFESTAT1 (ELFIN_NAND_BASENFESTAT1_OFFSET) #define NFMECC0 (ELFIN_NAND_BASENFMECC0_OFFSET) #define NFMECC1 (ELFIN_NAND_BASENFMECC1_OFFSET) #define NFSECC (ELFIN_NAND_BASENFSECC_OFFSET) #define NFMLCBITPT (ELFIN_NAND_BASENFMLCBITPT_OFFSET)#define NFECCCONF (ELFIN_NAND_ECC_BASENFECCCONF_OFFSET) #define NFECCCONT (ELFIN_NAND_ECC_BASENFECCCONT_OFFSET) #define NFECCSTAT (ELFIN_NAND_ECC_BASENFECCSTAT_OFFSET) #define NFECCSECSTAT (ELFIN_NAND_ECC_BASENFECCSECSTAT_OFFSET) #define NFECCPRGECC0 (ELFIN_NAND_ECC_BASENFECCPRGECC0_OFFSET) #define NFECCPRGECC1 (ELFIN_NAND_ECC_BASENFECCPRGECC1_OFFSET) #define NFECCPRGECC2 (ELFIN_NAND_ECC_BASENFECCPRGECC2_OFFSET) #define NFECCPRGECC3 (ELFIN_NAND_ECC_BASENFECCPRGECC3_OFFSET) #define NFECCPRGECC4 (ELFIN_NAND_ECC_BASENFECCPRGECC4_OFFSET) #define NFECCPRGECC5 (ELFIN_NAND_ECC_BASENFECCPRGECC5_OFFSET) #define NFECCPRGECC6 (ELFIN_NAND_ECC_BASENFECCPRGECC6_OFFSET) #define NFECCERL0 (ELFIN_NAND_ECC_BASENFECCERL0_OFFSET) #define NFECCERL1 (ELFIN_NAND_ECC_BASENFECCERL1_OFFSET) #define NFECCERL2 (ELFIN_NAND_ECC_BASENFECCERL2_OFFSET) #define NFECCERL3 (ELFIN_NAND_ECC_BASENFECCERL3_OFFSET) #define NFECCERL4 (ELFIN_NAND_ECC_BASENFECCERL4_OFFSET) #define NFECCERL5 (ELFIN_NAND_ECC_BASENFECCERL5_OFFSET) #define NFECCERL6 (ELFIN_NAND_ECC_BASENFECCERL6_OFFSET) #define NFECCERL7 (ELFIN_NAND_ECC_BASENFECCERL7_OFFSET) #define NFECCERP0 (ELFIN_NAND_ECC_BASENFECCERP0_OFFSET) #define NFECCERP1 (ELFIN_NAND_ECC_BASENFECCERP1_OFFSET) #define NFECCERP2 (ELFIN_NAND_ECC_BASENFECCERP2_OFFSET) #define NFECCERP3 (ELFIN_NAND_ECC_BASENFECCERP3_OFFSET) #define NFECCCONECC0 (ELFIN_NAND_ECC_BASENFECCCONECC0_OFFSET) #define NFECCCONECC1 (ELFIN_NAND_ECC_BASENFECCCONECC1_OFFSET) #define NFECCCONECC2 (ELFIN_NAND_ECC_BASENFECCCONECC2_OFFSET) #define NFECCCONECC3 (ELFIN_NAND_ECC_BASENFECCCONECC3_OFFSET) #define NFECCCONECC4 (ELFIN_NAND_ECC_BASENFECCCONECC4_OFFSET) #define NFECCCONECC5 (ELFIN_NAND_ECC_BASENFECCCONECC5_OFFSET) #define NFECCCONECC6 (ELFIN_NAND_ECC_BASENFECCCONECC6_OFFSET)#define NFCONF_REG __REG(ELFIN_NAND_BASENFCONF_OFFSET) #define NFCONT_REG __REG(ELFIN_NAND_BASENFCONT_OFFSET) #define NFCMD_REG __REG(ELFIN_NAND_BASENFCMMD_OFFSET) #define NFADDR_REG __REG(ELFIN_NAND_BASENFADDR_OFFSET) #define NFDATA_REG __REG(ELFIN_NAND_BASENFDATA_OFFSET) #define NFDATA8_REG __REGb(ELFIN_NAND_BASENFDATA_OFFSET) #define NFMECCDATA0_REG __REG(ELFIN_NAND_BASENFMECCDATA0_OFFSET) #define NFMECCDATA1_REG __REG(ELFIN_NAND_BASENFMECCDATA1_OFFSET) #define NFSECCDATA0_REG __REG(ELFIN_NAND_BASENFSECCDATA0_OFFSET) #define NFSBLK_REG __REG(ELFIN_NAND_BASENFSBLK_OFFSET) #define NFEBLK_REG __REG(ELFIN_NAND_BASENFEBLK_OFFSET) #define NFSTAT_REG __REG(ELFIN_NAND_BASENFSTAT_OFFSET) #define NFESTAT0_REG __REG(ELFIN_NAND_BASENFESTAT0_OFFSET) #define NFESTAT1_REG __REG(ELFIN_NAND_BASENFESTAT1_OFFSET) #define NFMECC0_REG __REG(ELFIN_NAND_BASENFMECC0_OFFSET) #define NFMECC1_REG __REG(ELFIN_NAND_BASENFMECC1_OFFSET) #define NFSECC_REG __REG(ELFIN_NAND_BASENFSECC_OFFSET) #define NFMLCBITPT_REG __REG(ELFIN_NAND_BASENFMLCBITPT_OFFSET)#define NFCONF_ECC_MLC (124)#define NFCONF_ECC_1BIT (023) #define NFCONF_ECC_4BIT (223) #define NFCONF_ECC_8BIT (123)#define NFCONT_ECC_ENC (118) #define NFCONT_WP (116) #define NFCONT_MECCLOCK (17) #define NFCONT_SECCLOCK (16) #define NFCONT_INITMECC (15) #define NFCONT_INITSECC (14) #define NFCONT_INITECC (NFCONT_INITMECC | NFCONT_INITSECC) #define NFCONT_CS (11) #define NFSTAT_ECCENCDONE (125) #define NFSTAT_ECCDECDONE (124) #define NFSTAT_RnB (10) #define NFESTAT0_ECCBUSY (131)/* Access Controller (TZPC) */ #define TZPC_DECPROT0SET_OFFSET 0x804 #define TZPC_DECPROT1SET_OFFSET 0x810 #define TZPC_DECPROT2SET_OFFSET 0x81C #define TZPC_DECPROT3SET_OFFSET 0x828/************************************************************** OneNAND Controller*************************************************************/ #define ELFIN_ONENAND_BASE 0xB0000000 #define ELFIN_ONENANDCON_BASE (ELFIN_ONENAND_BASE 0x600000)#define ONENAND_IF_CTRL_OFFSET 0x100 #define ONENAND_IF_CMD_OFFSET 0x104 #define ONENAND_IF_ASYNC_TIMING_CTRL_OFFSET 0x108 #define ONENAND_IF_STATUS_OFFSET 0x10C #define DMA_SRC_ADDR_OFFSET 0x400 #define DMA_SRC_CFG_OFFSET 0x404 #define DMA_DST_ADDR_OFFSET 0x408 #define DMA_DST_CFG_OFFSET 0x40C #define DMA_TRANS_SIZE_OFFSET 0x414 #define DMA_TRANS_CMD_OFFSET 0x418 #define DMA_TRANS_STATUS_OFFSET 0x41C #define DMA_TRANS_DIR_OFFSET 0x420 #define SQC_SAO_OFFSET 0x600 #define SQC_CMD_OFFSET 0x608 #define SQC_STATUS_OFFSET 0x60C #define SQC_CAO_OFFSET 0x610 #define SQC_REG_CTRL_OFFSET 0x614 #define SQC_REG_VAL_OFFSET 0x618 #define SQC_BRPAO0_OFFSET 0x620 #define SQC_BRPAO1_OFFSET 0x624 #define INTC_SQC_CLR_OFFSET 0x1000 #define INTC_DMA_CLR_OFFSET 0x1004 #define INTC_ONENAND_CLR_OFFSET 0x1008 #define INTC_SQC_MASK_OFFSET 0x1020 #define INTC_DMA_MASK_OFFSET 0x1024 #define INTC_ONENAND_MASK_OFFSET 0x1028 #define INTC_SQC_PEND_OFFSET 0x1040 #define INTC_DMA_PEND_OFFSET 0x1044 #define INTC_ONENAND_PEND_OFFSET 0x1048 #define INTC_SQC_STATUS_OFFSET 0x1060 #define INTC_DMA_STATUS_OFFSET 0x1064 #define INTC_ONENAND_STATUS_OFFSET 0x1068/** Memory controller*/ #define ELFIN_SROM_BASE 0xE8000000#define SROM_BW_REG __REG(ELFIN_SROM_BASE0x0) #define SROM_BC0_REG __REG(ELFIN_SROM_BASE0x4) #define SROM_BC1_REG __REG(ELFIN_SROM_BASE0x8) #define SROM_BC2_REG __REG(ELFIN_SROM_BASE0xC) #define SROM_BC3_REG __REG(ELFIN_SROM_BASE0x10) #define SROM_BC4_REG __REG(ELFIN_SROM_BASE0x14) #define SROM_BC5_REG __REG(ELFIN_SROM_BASE0x18)/** SDRAM Controller*/ #define APB_DMC_0_BASE 0xF0000000 #define APB_DMC_1_BASE 0xF1400000 #define ASYNC_MSYS_DMC0_BASE 0xF1E00000#define DMC_CONCONTROL 0x00 #define DMC_MEMCONTROL 0x04 #define DMC_MEMCONFIG0 0x08 #define DMC_MEMCONFIG1 0x0C #define DMC_DIRECTCMD 0x10 #define DMC_PRECHCONFIG 0x14 #define DMC_PHYCONTROL0 0x18 #define DMC_PHYCONTROL1 0x1C #define DMC_RESERVED 0x20 #define DMC_PWRDNCONFIG 0x28 #define DMC_TIMINGAREF 0x30 #define DMC_TIMINGROW 0x34 #define DMC_TIMINGDATA 0x38 #define DMC_TIMINGPOWER 0x3C #define DMC_PHYSTATUS 0x40 #define DMC_CHIP0STATUS 0x48 #define DMC_CHIP1STATUS 0x4C #define DMC_AREFSTATUS 0x50 #define DMC_MRSTATUS 0x54 #define DMC_PHYTEST0 0x58 #define DMC_PHYTEST1 0x5C #define DMC_QOSCONTROL0 0x60 #define DMC_QOSCONFIG0 0x64 #define DMC_QOSCONTROL1 0x68 #define DMC_QOSCONFIG1 0x6C #define DMC_QOSCONTROL2 0x70 #define DMC_QOSCONFIG2 0x74 #define DMC_QOSCONTROL3 0x78 #define DMC_QOSCONFIG3 0x7C #define DMC_QOSCONTROL4 0x80 #define DMC_QOSCONFIG4 0x84 #define DMC_QOSCONTROL5 0x88 #define DMC_QOSCONFIG5 0x8C #define DMC_QOSCONTROL6 0x90 #define DMC_QOSCONFIG6 0x94 #define DMC_QOSCONTROL7 0x98 #define DMC_QOSCONFIG7 0x9C #define DMC_QOSCONTROL8 0xA0 #define DMC_QOSCONFIG8 0xA4 #define DMC_QOSCONTROL9 0xA8 #define DMC_QOSCONFIG9 0xAC #define DMC_QOSCONTROL10 0xB0 #define DMC_QOSCONFIG10 0xB4 #define DMC_QOSCONTROL11 0xB8 #define DMC_QOSCONFIG11 0xBC #define DMC_QOSCONTROL12 0xC0 #define DMC_QOSCONFIG12 0xC4 #define DMC_QOSCONTROL13 0xC8 #define DMC_QOSCONFIG13 0xCC #define DMC_QOSCONTROL14 0xD0 #define DMC_QOSCONFIG14 0xD4 #define DMC_QOSCONTROL15 0xD8 #define DMC_QOSCONFIG15 0xDC/* * Memory Chip direct command *//****************************************************************Definitions for memory configurationSet memory configurationactive_chips 1b0 (1 chip)qos_master_chip 3b000(ARID[3:0])memory burst 3b010(burst 4)stop_mem_clock 1b0(disable dynamical stop)auto_power_down 1b0(disable auto power-down mode)power_down_prd 6b00_0000(0 cycle for auto power-down)ap_bit 1b0 (bit position of auto-precharge is 10)row_bits 3b010(# row address 13)column_bits 3b010(# column address 10 )Set user configuration2b10SDRAM/mSDRAM, 2b11DDR, 2b01mDDRSet chip select for chip [n]row bank control, bank address 0x3000_0000 ~ 0x37ff_ffffCHIP_[n]_CFG0x30F8, 30: ADDR[31:24], F8: Mask[31:24] ******************************************************************/#define INF_REG_BASE 0xE010F000#define INF_REG0_REG __REG(INF_REG_BASEINF_REG0_OFFSET) #define INF_REG1_REG __REG(INF_REG_BASEINF_REG1_OFFSET) #define INF_REG2_REG __REG(INF_REG_BASEINF_REG2_OFFSET) #define INF_REG3_REG __REG(INF_REG_BASEINF_REG3_OFFSET) #define INF_REG4_REG __REG(INF_REG_BASEINF_REG4_OFFSET) #define INF_REG5_REG __REG(INF_REG_BASEINF_REG5_OFFSET) #define INF_REG6_REG __REG(INF_REG_BASEINF_REG6_OFFSET) #define INF_REG7_REG __REG(INF_REG_BASEINF_REG7_OFFSET)#define NFCONF_VAL (712)|(78)|(74)|(03)|(02)|(11)|(00) #define NFCONT_VAL (0x123)|(0x122)|(018)|(017)|(016)|(010)|(09)|(08)|(07)|(06)|(0x21)|(10) #define MP03CON_VAL (129)|(125)|(121)|(117)|(113)|(19)|(15)|(11)#define ELFIN_TZPC0_BASE 0xF1500000 #define ELFIN_TZPC1_BASE 0xFAD00000 #define ELFIN_TZPC2_BASE 0xE0600000 #define ELFIN_TZPC3_BASE 0xE1C00000 sdram_init.S #include s5pv210.h#if 1 #define DMC0_MEMCONTROL 0x00202400 // MemControl BL4, 1Chip, DDR2 Type, dynamic self refresh, force precharge, dynamic power down off#define DMC0_MEMCONFIG_0 0x20F01323 // MemConfig0 256MB config, 8 banks,Mapping Method[12:15]0:linear, 1:linterleaved, 2:Mixed #define DMC0_MEMCONFIG_1 0x30F00312 // MemConfig1 默认值#define DMC0_TIMINGA_REF 0x00000618 // TimingAref 7.8us*133MHz1038(0x40E), 100MHz780(0x30C), 20MHz156(0x9C), 10MHz78(0x4E) #define DMC0_TIMING_ROW 0x28233287 // TimingRow for 200MHz #define DMC0_TIMING_DATA 0x23240304 // TimingData CL3 #define DMC0_TIMING_PWR 0x09C80232 // TimingPower#define DMC1_MEMCONTROL 0x00202400 // MemControl BL4, 2 chip, DDR2 type, dynamic self refresh, force precharge, dynamic power down off#define DMC1_MEMCONFIG_0 0x40F01323 // MemConfig0 512MB config, 8 banks,Mapping Method[12:15]0:linear, 1:linterleaved, 2:Mixed #define DMC1_MEMCONFIG_1 0x60E00312 // MemConfig1#define DMC1_TIMINGA_REF 0x00000618 // TimingAref 7.8us*133MHz1038(0x40E), 100MHz780(0x30C), 20MHz156(0x9C), 10MHz78(0x4 #define DMC1_TIMING_ROW 0x28233289 // TimingRow for 200MHz #define DMC1_TIMING_DATA 0x23240304 // TimingData CL3 #define DMC1_TIMING_PWR 0x08280232 // TimingPower#endif#if 0#define DMC0_MEMCONTROL 0x00212400 // MemControl BL4, 1Chip, DDR2 Type, dynamic self refresh, force precharge, dynamic power down off#define DMC0_MEMCONFIG_0 0x20E01323 // MemConfig0 512MB config, 8 banks,Mapping Method[12:15]0:linear, 1:linterleaved, 2:Mixed #define DMC0_MEMCONFIG_1 0x40F01323 // MemConfig1#define DMC0_TIMINGA_REF 0x00000618 // TimingAref 7.8us*133MHz1038(0x40E), 100MHz780(0x30C), 20MHz156(0x9C), 10MHz78(0x4E) #define DMC0_TIMING_ROW 0x28233287 // TimingRow for 200MHz #define DMC0_TIMING_DATA 0x23240304 // TimingData CL3 #define DMC0_TIMING_PWR 0x09C80232 // TimingPower#define DMC1_MEMCONTROL 0x00202400 // MemControl BL4, 2 chip, DDR2 type, dynamic self refresh, force precharge, dynamic power down off#define DMC1_MEMCONFIG_0 0x40C01323 // MemConfig0 512MB config, 8 banks,Mapping Method[12:15]0:linear, 1:linterleaved, 2:Mixed #define DMC1_MEMCONFIG_1 0x00E01323 // MemConfig1#define DMC1_TIMINGA_REF 0x00000618 // TimingAref 7.8us*133MHz1038(0x40E), 100MHz780(0x30C), 20MHz156(0x9C), 10MHz78(0x4 #define DMC1_TIMING_ROW 0x28233289 // TimingRow for 200MHz #define DMC1_TIMING_DATA 0x23240304 // TimingData CL3 #define DMC1_TIMING_PWR 0x08280232 // TimingPower#endif.global sdram_asm_initsdram_asm_init:ldr r0, 0xf1e00000ldr r1, 0x0str r1, [r0, #0x0]/* DMC0 Drive Strength (Setting 2X) */ldr r0, ELFIN_GPIO_BASEldr r1, 0x0000AAAAstr r1, [r0, #MP1_0DRV_SR_OFFSET] // 寄存器中对应0b10就是2Xldr r1, 0x0000AAAAstr r1, [r0, #MP1_1DRV_SR_OFFSET]ldr r1, 0x0000AAAAstr r1, [r0, #MP1_2DRV_SR_OFFSET]ldr r1, 0x0000AAAAstr r1, [r0, #MP1_3DRV_SR_OFFSET]ldr r1, 0x0000AAAAstr r1, [r0, #MP1_4DRV_SR_OFFSET]ldr r1, 0x0000AAAAstr r1, [r0, #MP1_5DRV_SR_OFFSET]ldr r1, 0x0000AAAAstr r1, [r0, #MP1_6DRV_SR_OFFSET]ldr r1, 0x0000AAAAstr r1, [r0, #MP1_7DRV_SR_OFFSET]ldr r1, 0x00002AAAstr r1, [r0, #MP1_8DRV_SR_OFFSET]/* DMC1 Drive Strength (Setting 2X) */ldr r0, ELFIN_GPIO_BASEldr r1, 0x0000AAAAstr r1, [r0, #MP2_0DRV_SR_OFFSET]ldr r1, 0x0000AAAAstr r1, [r0, #MP2_1DRV_SR_OFFSET]ldr r1, 0x0000AAAAstr r1, [r0, #MP2_2DRV_SR_OFFSET]ldr r1, 0x0000AAAAstr r1, [r0, #MP2_3DRV_SR_OFFSET]ldr r1, 0x0000AAAAstr r1, [r0, #MP2_4DRV_SR_OFFSET]ldr r1, 0x0000AAAAstr r1, [r0, #MP2_5DRV_SR_OFFSET]ldr r1, 0x0000AAAAstr r1, [r0, #MP2_6DRV_SR_OFFSET]ldr r1, 0x0000AAAAstr r1, [r0, #MP2_7DRV_SR_OFFSET]ldr r1, 0x00002AAAstr r1, [r0, #MP2_8DRV_SR_OFFSET]/* DMC0 initialization at single Type*/ldr r0, APB_DMC_0_BASEldr r1, 0x00101000 PhyControl0 DLL parameter setting, manual 0x00101000str r1, [r0, #DMC_PHYCONTROL0]ldr r1, 0x00000086 PhyControl1 DLL parameter setting, LPDDR/LPDDR2 Casestr r1, [r0, #DMC_PHYCONTROL1]ldr r1, 0x00101002 PhyControl0 DLL onstr r1, [r0, #DMC_PHYCONTROL0]ldr r1, 0x00101003 PhyControl0 DLL startstr r1, [r0, #DMC_PHYCONTROL0]find_lock_val:ldr r1, [r0, #DMC_PHYSTATUS] Load Phystatus register valueand r2, r1, #0x7cmp r2, #0x7 Loop until DLL is lockedbne find_lock_valand r1, #0x3fc0 mov r2, r1, LSL #18orr r2, r2, #0x100000orr r2 ,r2, #0x1000orr r1, r2, #0x3 Force Value lockingstr r1, [r0, #DMC_PHYCONTROL0]#if 0 /* Memory margin test 10.01.05 */orr r1, r2, #0x1 DLL offstr r1, [r0, #DMC_PHYCONTROL0] #endif/* setting DDR2 */ldr r1, 0x0FFF2010 ConControl auto refresh offstr r1, [r0, #DMC_CONCONTROL]ldr r1, DMC0_MEMCONTROL MemControl BL4, 1 chip, DDR2 type, dynamic self refresh, force precharge, dynamic power down offstr r1, [r0, #DMC_MEMCONTROL]ldr r1, DMC0_MEMCONFIG_0 MemConfig0 256MB config, 8 banks,Mapping Method[12:15]0:linear, 1:linterleaved, 2:Mixedstr r1, [r0, #DMC_MEMCONFIG0]ldr r1, DMC0_MEMCONFIG_1 MemConfig1str r1, [r0, #DMC_MEMCONFIG1]ldr r1, 0xFF000000 PrechConfigstr r1, [r0, #DMC_PRECHCONFIG]ldr r1, DMC0_TIMINGA_REF TimingAref 7.8us*133MHz1038(0x40E), 100MHz780(0x30C), 20MHz156(0x9C), 10MHz78(0x4E)str r1, [r0, #DMC_TIMINGAREF]ldr r1, DMC0_TIMING_ROW TimingRow for 200MHzstr r1, [r0, #DMC_TIMINGROW]ldr r1, DMC0_TIMING_DATA TimingData CL3str r1, [r0, #DMC_TIMINGDATA]ldr r1, DMC0_TIMING_PWR TimingPowerstr r1, [r0, #DMC_TIMINGPOWER]ldr r1, 0x07000000 DirectCmd chip0 Deselectstr r1, [r0, #DMC_DIRECTCMD]ldr r1, 0x01000000 DirectCmd chip0 PALLstr r1, [r0, #DMC_DIRECTCMD]ldr r1, 0x00020000 DirectCmd chip0 EMRS2str r1, [r0, #DMC_DIRECTCMD]ldr r1, 0x00030000 DirectCmd chip0 EMRS3str r1, [r0, #DMC_DIRECTCMD]ldr r1, 0x00010400 DirectCmd chip0 EMRS1 (MEM DLL on, DQS# disable)str r1, [r0, #DMC_DIRECTCMD]ldr r1, 0x00000542 DirectCmd chip0 MRS (MEM DLL reset) CL4, BL4str r1, [r0, #DMC_DIRECTCMD]ldr r1, 0x01000000 DirectCmd chip0 PALLstr r1, [r0, #DMC_DIRECTCMD]ldr r1, 0x05000000 DirectCmd chip0 REFAstr r1, [r0, #DMC_DIRECTCMD]ldr r1, 0x05000000 DirectCmd chip0 REFAstr r1, [r0, #DMC_DIRECTCMD]ldr r1, 0x00000442 DirectCmd chip0 MRS (MEM DLL unreset)str r1, [r0, #DMC_DIRECTCMD]ldr r1, 0x00010780 DirectCmd chip0 EMRS1 (OCD default)str r1, [r0, #DMC_DIRECTCMD]ldr r1, 0x00010400 DirectCmd chip0 EMRS1 (OCD exit)str r1, [r0, #DMC_DIRECTCMD]ldr r1, 0x07100000 DirectCmd chip1 Deselectstr r1, [r0, #DMC_DIRECTCMD]ldr r1, 0x01100000 DirectCmd chip1 PALLstr r1, [r0, #DMC_DIRECTCMD]ldr r1, 0x00120000 DirectCmd chip1 EMRS2str r1, [r0, #DMC_DIRECTCMD]ldr r1, 0x00130000 DirectCmd chip1 EMRS3str r1, [r0, #DMC_DIRECTCMD]ldr r1, 0x00110400 DirectCmd chip1 EMRS1 (MEM DLL on, DQS# disable)str r1, [r0, #DMC_DIRECTCMD]ldr r1, 0x00100542 DirectCmd chip1 MRS (MEM DLL reset) CL4, BL4str r1, [r0, #DMC_DIRECTCMD]ldr r1, 0x01100000 DirectCmd chip1 PALLstr r1, [r0, #DMC_DIRECTCMD]ldr r1, 0x05100000 DirectCmd chip1 REFAstr r1, [r0, #DMC_DIRECTCMD]ldr r1, 0x05100000 DirectCmd chip1 REFAstr r1, [r0, #DMC_DIRECTCMD]ldr r1, 0x00100442 DirectCmd chip1 MRS (MEM DLL unreset)str r1, [r0, #DMC_DIRECTCMD]ldr r1, 0x00110780 DirectCmd chip1 EMRS1 (OCD default)str r1, [r0, #DMC_DIRECTCMD]ldr r1, 0x00110400 DirectCmd chip1 EMRS1 (OCD exit)str r1, [r0, #DMC_DIRECTCMD]ldr r1, 0x0FF02030 ConControl auto refresh onstr r1, [r0, #DMC_CONCONTROL]ldr r1, 0xFFFF00FF PwrdnConfigstr r1, [r0, #DMC_PWRDNCONFIG]ldr r1, 0x00202400 MemControl BL4, 2 chip, DDR2 type, dynamic self refresh, force precharge, dynamic power down offstr r1, [r0, #DMC_MEMCONTROL]// 上面是DRAM0初始化步骤 /*******************************************************************************************/ // 下面是DRAM1初始化步骤两者没有联系是并列的。/* DMC1 initialization */ldr r0, APB_DMC_1_BASEldr r1, 0x00101000 Phycontrol0 DLL parameter settingstr r1, [r0, #DMC_PHYCONTROL0]ldr r1, 0x00000086 Phycontrol1 DLL parameter settingstr r1, [r0, #DMC_PHYCONTROL1]ldr r1, 0x00101002 PhyControl0 DLL onstr r1, [r0, #DMC_PHYCONTROL0]ldr r1, 0x00101003 PhyControl0 DLL startstr r1, [r0, #DMC_PHYCONTROL0]find_lock_val1:ldr r1, [r0, #DMC_PHYSTATUS] Load Phystatus register valueand r2, r1, #0x7cmp r2, #0x7 Loop until DLL is lockedbne find_lock_val1and r1, #0x3fc0 mov r2, r1, LSL #18orr r2, r2, #0x100000orr r2, r2, #0x1000orr r1, r2, #0x3 Force Value lockingstr r1, [r0, #DMC_PHYCONTROL0]#if 0 /* Memory margin test 10.01.05 */orr r1, r2, #0x1 DLL offstr r1, [r0, #DMC_PHYCONTROL0] #endif/* settinf fot DDR2 */ldr r0, APB_DMC_1_BASEldr r1, 0x0FFF2010 auto refresh offstr r1, [r0, #DMC_CONCONTROL]ldr r1, DMC1_MEMCONTROL MemControl BL4, 2 chip, DDR2 type, dynamic self refresh, force precharge, dynamic power down offstr r1, [r0, #DMC_MEMCONTROL]ldr r1, DMC1_MEMCONFIG_0 MemConfig0 512MB config, 8 banks,Mapping Method[12:15]0:linear, 1:linterleaved, 2:Mixedstr r1, [r0, #DMC_MEMCONFIG0]ldr r1, DMC1_MEMCONFIG_1 MemConfig1str r1, [r0, #DMC_MEMCONFIG1]ldr r1, 0xFF000000str r1, [r0, #DMC_PRECHCONFIG]ldr r1, DMC1_TIMINGA_REF TimingAref 7.8us*133MHz1038(0x40E), 100MHz780(0x30C), 20MHz156(0x9C), 10MHz78(0x4str r1, [r0, #DMC_TIMINGAREF]ldr r1, DMC1_TIMING_ROW TimingRow for 200MHzstr r1, [r0, #DMC_TIMINGROW]ldr r1, DMC1_TIMING_DATA TimingData CL3str r1, [r0, #DMC_TIMINGDATA]ldr r1, DMC1_TIMING_PWR TimingPowerstr r1, [r0, #DMC_TIMINGPOWER]ldr r1, 0x07000000 DirectCmd chip0 Deselectstr r1, [r0, #DMC_DIRECTCMD]ldr r1, 0x01000000 DirectCmd chip0 PALLstr r1, [r0, #DMC_DIRECTCMD]ldr r1, 0x00020000 DirectCmd chip0 EMRS2str r1, [r0, #DMC_DIRECTCMD]ldr r1, 0x00030000 DirectCmd chip0 EMRS3str r1, [r0, #DMC_DIRECTCMD]ldr r1, 0x00010400 DirectCmd chip0 EMRS1 (MEM DLL on, DQS# disable)str r1, [r0, #DMC_DIRECTCMD]ldr r1, 0x00000542 DirectCmd chip0 MRS (MEM DLL reset) CL4, BL4str r1, [r0, #DMC_DIRECTCMD]ldr r1, 0x01000000 DirectCmd chip0 PALLstr r1, [r0, #DMC_DIRECTCMD]ldr r1, 0x05000000 DirectCmd chip0 REFAstr r1, [r0, #DMC_DIRECTCMD]ldr r1, 0x05000000 DirectCmd chip0 REFAstr r1, [r0, #DMC_DIRECTCMD]ldr r1, 0x00000442 DirectCmd chip0 MRS (MEM DLL unreset)str r1, [r0, #DMC_DIRECTCMD]ldr r1, 0x00010780 DirectCmd chip0 EMRS1 (OCD default)str r1, [r0, #DMC_DIRECTCMD]ldr r1, 0x00010400 DirectCmd chip0 EMRS1 (OCD exit)str r1, [r0, #DMC_DIRECTCMD]ldr r1, 0x07100000 DirectCmd chip1 Deselectstr r1, [r0, #DMC_DIRECTCMD]ldr r1, 0x01100000 DirectCmd chip1 PALLstr r1, [r0, #DMC_DIRECTCMD]ldr r1, 0x00120000 DirectCmd chip1 EMRS2str r1, [r0, #DMC_DIRECTCMD]ldr r1, 0x00130000 DirectCmd chip1 EMRS3str r1, [r0, #DMC_DIRECTCMD]ldr r1, 0x00110440 DirectCmd chip1 EMRS1 (MEM DLL on, DQS# disable)str r1, [r0, #DMC_DIRECTCMD]ldr r1, 0x00100542 DirectCmd chip1 MRS (MEM DLL reset) CL4, BL4str r1, [r0, #DMC_DIRECTCMD]ldr r1, 0x01100000 DirectCmd chip1 PALLstr r1, [r0, #DMC_DIRECTCMD]ldr r1, 0x05100000 DirectCmd chip1 REFAstr r1, [r0, #DMC_DIRECTCMD]ldr r1, 0x05100000 DirectCmd chip1 REFAstr r1, [r0, #DMC_DIRECTCMD]ldr r1, 0x00100442 DirectCmd chip1 MRS (MEM DLL unreset)str r1, [r0, #DMC_DIRECTCMD]ldr r1, 0x00110780 DirectCmd chip1 EMRS1 (OCD default)str r1, [r0, #DMC_DIRECTCMD]ldr r1, 0x00110400 DirectCmd chip1 EMRS1 (OCD exit)str r1, [r0, #DMC_DIRECTCMD]ldr r1, 0x0FF02030 ConControl auto refresh onstr r1, [r0, #DMC_CONCONTROL]ldr r1, 0xFFFF00FF PwrdnConfigstr r1, [r0, #DMC_PWRDNCONFIG]ldr r1, DMC1_MEMCONTROL MemControl BL4, 2 chip, DDR2 type, dynamic self refresh, force precharge, dynamic power down offstr r1, [r0, #DMC_MEMCONTROL]// 函数返回mov pc, lr load_sd_bl2_2_ddr.c #define CHANNEL 2 #define SD_START_BLOCK 45 #define SD_BLOCK_COUNT (2048*2) #define DDR_START_ADDR 0x23E00000 #define WITH_INIT 0typedef unsigned int bool;typedef bool(*copy_sdmmc_to_mem)(int, unsigned int, unsigned short, unsigned int*, bool);typedef void (*bl2_type)();void copy_bl2_2_ddr() {//the func is copy bl2 to ddr//0xD0037F98 is the address of cpoy func //define func copy_sdmmc_to_mem copy (copy_sdmmc_to_mem) (*((unsigned int *)0xD0037F98));//use funccopy(CHANNEL, SD_START_BLOCK, SD_BLOCK_COUNT, (unsigned int *)DDR_START_ADDR,WITH_INIT);//jump ddr,work bl2bl2_type bl2 (bl2_type) DDR_START_ADDR;bl2(); } link.lds SECTIONS {. 0xd0020010;.text : {start.o* (.text)}.data : {* (.data)}.bss : {* (.bss)} } Makefile CC arm-linux-gcc LD arm-linux-ld OBJCOPY arm-linux-objcopy OBJDUMP arm-linux-objdumpINCDIR : $(shell pwd)#预处理器的flagflag就是编译器可选的选项 CPPFLAGS : -nostdlib -nostdinc -I$(INCDIR)/include #C编译器的flag CFLAGS : -Wall -O2 -fno-builtinexport CC LD OBJCOPY OBJDUMP CPPFLAGS CFLAGSobjs : start.o load_sd_bl2_2_ddr.o sdram_init.o bl1.bin:$(objs)$(LD) -Tlink.lds -o bl1.elf $^$(OBJCOPY) -O binary bl1.elf bl1.bin$(OBJDUMP) -D bl1.elf bl1.disgcc mkv210.c -o mkv210./mkv210 bl1.bin sd1.bin%.o:%.S$(CC) $(CPPFLAGS) $(CFLAGS) -o $ $ -c%.o:%.c$(CC) $(CPPFLAGS) $(CFLAGS) -o $ $ -cclean:rm *.o *.elf *.bin *.dis mkv210 -f bl2: start.S .global _start _start:ldr pc,mainb . main.c #include lcd.h #include 1024600.hint main() {lcd_init();//init_background(WHITE);//lcd_draw_line(0, 479, 799, 0, BLACK);//lcd_draw_circle(300, 500, 30, BLACK);//lcd_draw_string(0, 0, BLACK, Hello Word !);lcd_appear_picture(gImage_1024600);return 0; } lcd.h #define BLUE 0x0000FF #define RED 0xFF0000 #define GREEN 0x00FF00 #define WHITE 0xFFFFFF #define BLACK 0x000000void lcd_init();void init_background(unsigned int color);void lcd_draw_line(unsigned int x1, unsigned int y1, unsigned int x2, unsigned int y2, unsigned int color);void lcd_draw_circle(unsigned int centerX, unsigned int centerY, unsigned int radius, unsigned int color);void lcd_draw_string(unsigned int x, unsigned int y, unsigned int color, unsigned char *str);void lcd_appear_picture(const unsigned char *pData); lcd.c #include ascii.htypedef unsigned int u32; typedef unsigned short u16;#define GPF0CON 0xE0200120 #define GPF1CON 0xE0200140 #define GPF2CON 0xE0200160 #define GPF3CON 0xE0200180#define GPD0CON 0xE02000A0 #define GPD0DAT 0xE02000A4#define rGPF0CON (*(volatile unsigned int *)GPF0CON) #define rGPF1CON (*(volatile unsigned int *)GPF1CON) #define rGPF2CON (*(volatile unsigned int *)GPF2CON) #define rGPF3CON (*(volatile unsigned int *)GPF3CON) #define rGPD0CON (*(volatile unsigned int *)GPD0CON) #define rGPD0DAT (*(volatile unsigned int *)GPD0DAT)#define DISPLAY_CONTROL 0xe0107008 #define VIDCON0 0xF8000000 #define VIDCON1 0xF8000004 #define VIDTCON0 0xF8000010 #define VIDTCON1 0xF8000014 #define VIDTCON2 0xF8000018 #define WINCON0 0xF8000020 #define SHADOWCON 0xF8000034 #define VIDOSD0A 0xF8000040 #define VIDOSD0B 0xF8000044 #define VIDOSD0C 0xF8000048 #define VIDW00ADD0B0 0xF80000A0 #define VIDW00ADD1B0 0xF80000D0#define rDISPLAY_CONTROL (*(volatile unsigned int *)DISPLAY_CONTROL) #define rVIDCON0 (*(volatile unsigned int *)VIDCON0) #define rVIDCON1 (*(volatile unsigned int *)VIDCON1) #define rVIDTCON0 (*(volatile unsigned int *)VIDTCON0) #define rVIDTCON1 (*(volatile unsigned int *)VIDTCON1) #define rVIDTCON2 (*(volatile unsigned int *)VIDTCON2) #define rWINCON0 (*(volatile unsigned int *)WINCON0) #define rSHADOWCON (*(volatile unsigned int *)SHADOWCON) #define rVIDOSD0A (*(volatile unsigned int *)VIDOSD0A) #define rVIDOSD0B (*(volatile unsigned int *)VIDOSD0B) #define rVIDOSD0C (*(volatile unsigned int *)VIDOSD0C) #define rVIDW00ADD0B0 (*(volatile unsigned int *)VIDW00ADD0B0) #define rVIDW00ADD1B0 (*(volatile unsigned int *)VIDW00ADD1B0) #define HSPW (40) #define HBPD (10 - 1) #define HFPD (240 - 1) #define VSPW (20) #define VBPD (10 - 1) #define VFPD (30 - 1)//FB地址 #define FB_ADDR (0x23000000) #define ROW (600) #define COL (1024) #define HOZVAL (COL-1) #define LINEVAL (ROW-1)#define XSIZE COL #define YSIZE ROW#define LeftTopX 0 #define LeftTopY 0 #define RightBotX (1024 - 1) #define RightBotY (600 - 1)u32 *pfb (u32 *)FB_ADDR;void lcd_init() {//set gpio as lcdrGPF0CON 0x22222222;rGPF1CON 0x22222222;rGPF2CON 0x22222222;rGPF3CON 0x22222222;//set gpio as PWMTOUT0, open background lightrGPD0CON ~(0xf);rGPD0CON | (1);rGPD0DAT ~(1);//set lcd crontol(FIMD) connect outer port(180,rgb,yuv)rDISPLAY_CONTROL 2;//rDISPLAY_CONTROL 3;//set RGB interface,RGB parallel format,HCLK_DSYS(166MHz)rVIDCON0 ~((326)|(118)|(12));//enable lcdrVIDCON0 | ((1)|(11));//set div(VCLK 166Mhz/(41) 33Mhz) and select divrVIDCON0 | ((46) | (14));//set IVSYNC and IHSYNC high level(Inverted)rVIDCON1 | ((15) | (16));//set Time sequencerVIDTCON0 VBPD16 | VFPD8 | VSPW0;rVIDTCON1 HBPD16 | HFPD8 | HSPW0;//set lcd width and length rVIDTCON2 ((LINEVAL 11) | (HOZVAL 0));//enable window0 and set 24bpp(RGB888)rWINCON0 | 1;rWINCON0 ~(0xf 2);rWINCON0 | (0xB2) | (115);//set lcd coordinate and rangerVIDOSD0A ((LeftTopX11) | (LeftTopY 0));rVIDOSD0B ((RightBotX11) | (RightBotY 0));rVIDOSD0C ((LINEVAL 1) * (HOZVAL 1));//set Video frame start and end address(buffer)rVIDW00ADD0B0 FB_ADDR;rVIDW00ADD1B0 (((HOZVAL 1)*4 0) * (LINEVAL 1)) (0xffffff);//enable channel 0 to transmit datarSHADOWCON 0x1; }//set pic color static void lcd_draw_pic_color(u32 x,u32 y,u32 color) {*(pfb COL * y x) color; }//init lcd background void init_background(unsigned int color) {u32 i, j;for (j0; jROW; j){for (i0; iCOL; i){lcd_draw_pic_color(i, j, color);}} }//glib draw line,dot_1(x1,y1),dot_2(x2,y2) void lcd_draw_line(unsigned int x1, unsigned int y1, unsigned int x2, unsigned int y2, unsigned int color) {int dx,dy,e;dxx2-x1; dyy2-y1;if(dx0){if(dy 0) // dy0{if(dxdy) // 1/8 octant{edy-dx/2; while(x1x2){lcd_draw_pic_color(x1,y1,color);if(e0){y11;e-dx;}x11;edy;}}else // 2/8 octant{edx-dy/2;while(y1y2){lcd_draw_pic_color(x1,y1,color);if(e0){x11;e-dy;}y11;edx;}}}else // dy0{dy-dy; // dyabs(dy)if(dxdy) // 8/8 octant{edy-dx/2;while(x1x2){lcd_draw_pic_color(x1,y1,color);if(e0){y1-1;e-dx;}x11;edy;}}else // 7/8 octant{edx-dy/2;while(y1y2){lcd_draw_pic_color(x1,y1,color);if(e0){x11;e-dy;}y1-1;edx;}}}}else //dx0{dx-dx; //dxabs(dx)if(dy 0) // dy0{if(dxdy) // 4/8 octant{edy-dx/2;while(x1x2){lcd_draw_pic_color(x1,y1,color);if(e0){y11;e-dx;}x1-1;edy;}}else // 3/8 octant{edx-dy/2;while(y1y2){lcd_draw_pic_color(x1,y1,color);if(e0){x1-1;e-dy;}y11;edx;}}}else // dy0{dy-dy; // dyabs(dy)if(dxdy) // 5/8 octant{edy-dx/2;while(x1x2){lcd_draw_pic_color(x1,y1,color);if(e0){y1-1;e-dx;}x1-1;edy;}}else // 6/8 octant{edx-dy/2;while(y1y2){lcd_draw_pic_color(x1,y1,color);if(e0){x1-1;e-dy;}y1-1;edx;}}}} }//draw circle , Center of a circle (centerX, centerY),radius,color void lcd_draw_circle(unsigned int centerX, unsigned int centerY, unsigned int radius, unsigned int color) {int x,y ;int tempX,tempY;;int SquareOfR radius*radius;for(y0; yXSIZE; y){for(x0; xYSIZE; x){if(ycenterY xcenterX){tempYcenterY-y;tempXcenterX-x; }else if(ycenterY xcenterX){tempYcenterY-y;tempXx-centerX; }else if(ycenterY xcenterX){tempYy-centerY;tempXcenterX-x; }else{tempY y-centerY;tempX x-centerX;}if ((tempY*tempYtempX*tempX)SquareOfR)lcd_draw_pic_color(x, y, color);}} }//draw letter,posion (x, y),color,data(Font information) static void show_8_16(unsigned int x, unsigned int y, unsigned int color, unsigned char *data) { //count:recodes pix that usingint i, j, count 0; for (jy; j(y16); j) { for (ix; i(x8); i) { if (iXSIZE jYSIZE) { if (data[count/8] (1(count%8))) lcd_draw_pic_color(i, j, color);} count; } } } //draw string,start posion(x,y) void lcd_draw_string(unsigned int x, unsigned int y, unsigned int color, unsigned char *str) {int i; unsigned char *ch;for (i0; str[i]!\0; i) { ch (unsigned char *)ascii_8_16[(unsigned char)str[i]-0x20];show_8_16(x, y, color, ch); x 8;if (x XSIZE){x - XSIZE; //\ry 16; //\n}} }//appear the picture of 800×480,and the picture of font information in pData void lcd_appear_picture(const unsigned char *pData) {u32 x, y, color, p 0;for (y0; y600; y){for (x0; x1024; x){color ((pData[p2] 0) | (pData[p1] 8) | (pData[p0] 16));lcd_draw_pic_color(x, y, color);p 3;}} } 1024600.h ascii.h #ifndef __ASCII_H__ #define __ASCII_H__//以下字模与ASCII对应是只要将 A-0x20就可以得到A的字模了 //高8*5宽 ASCII码 //提取方式:纵向取模,字节倒序 //以下是8*16的 //高是16 //横向扫描 const unsigned char ascii_8_16[95][16] { {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/* ,0*/ {0x00,0x00,0x00,0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x00,0x00,0x18,0x18,0x00,0x00},/*!,1*/ {0x00,0x48,0x6C,0x24,0x12,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*,2*/ {0x00,0x00,0x00,0x24,0x24,0x24,0x7F,0x12,0x12,0x12,0x7F,0x12,0x12,0x12,0x00,0x00},/*#,3*/ {0x00,0x00,0x08,0x1C,0x2A,0x2A,0x0A,0x0C,0x18,0x28,0x28,0x2A,0x2A,0x1C,0x08,0x08},/*{1}quot;,4*/ {0x00,0x00,0x00,0x22,0x25,0x15,0x15,0x15,0x2A,0x58,0x54,0x54,0x54,0x22,0x00,0x00},/*%,5*/ {0x00,0x00,0x00,0x0C,0x12,0x12,0x12,0x0A,0x76,0x25,0x29,0x11,0x91,0x6E,0x00,0x00},/*,6*/ {0x00,0x06,0x06,0x04,0x03,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*,7*/ {0x00,0x40,0x20,0x10,0x10,0x08,0x08,0x08,0x08,0x08,0x08,0x10,0x10,0x20,0x40,0x00},/*(,8*/ {0x00,0x02,0x04,0x08,0x08,0x10,0x10,0x10,0x10,0x10,0x10,0x08,0x08,0x04,0x02,0x00},/*),9*/ {0x00,0x00,0x00,0x00,0x08,0x08,0x6B,0x1C,0x1C,0x6B,0x08,0x08,0x00,0x00,0x00,0x00},/**,10*/ {0x00,0x00,0x00,0x00,0x08,0x08,0x08,0x08,0x7F,0x08,0x08,0x08,0x08,0x00,0x00,0x00},/*,11*/ {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x06,0x06,0x04,0x03},/*,,12*/ {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xFE,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*-,13*/ {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x06,0x06,0x00,0x00},/*.,14*/ {0x00,0x00,0x80,0x40,0x40,0x20,0x20,0x10,0x10,0x08,0x08,0x04,0x04,0x02,0x02,0x00},/*/,15*/ {0x00,0x00,0x00,0x18,0x24,0x42,0x42,0x42,0x42,0x42,0x42,0x42,0x24,0x18,0x00,0x00},/*0,16*/ {0x00,0x00,0x00,0x08,0x0E,0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x3E,0x00,0x00},/*1,17*/ {0x00,0x00,0x00,0x3C,0x42,0x42,0x42,0x20,0x20,0x10,0x08,0x04,0x42,0x7E,0x00,0x00},/*2,18*/ {0x00,0x00,0x00,0x3C,0x42,0x42,0x20,0x18,0x20,0x40,0x40,0x42,0x22,0x1C,0x00,0x00},/*3,19*/ {0x00,0x00,0x00,0x20,0x30,0x28,0x24,0x24,0x22,0x22,0x7E,0x20,0x20,0x78,0x00,0x00},/*4,20*/ {0x00,0x00,0x00,0x7E,0x02,0x02,0x02,0x1A,0x26,0x40,0x40,0x42,0x22,0x1C,0x00,0x00},/*5,21*/ {0x00,0x00,0x00,0x38,0x24,0x02,0x02,0x1A,0x26,0x42,0x42,0x42,0x24,0x18,0x00,0x00},/*6,22*/ {0x00,0x00,0x00,0x7E,0x22,0x22,0x10,0x10,0x08,0x08,0x08,0x08,0x08,0x08,0x00,0x00},/*7,23*/ {0x00,0x00,0x00,0x3C,0x42,0x42,0x42,0x24,0x18,0x24,0x42,0x42,0x42,0x3C,0x00,0x00},/*8,24*/ {0x00,0x00,0x00,0x18,0x24,0x42,0x42,0x42,0x64,0x58,0x40,0x40,0x24,0x1C,0x00,0x00},/*9,25*/ {0x00,0x00,0x00,0x00,0x00,0x00,0x18,0x18,0x00,0x00,0x00,0x00,0x18,0x18,0x00,0x00},/*:,26*/ {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x08,0x00,0x00,0x00,0x00,0x00,0x08,0x08,0x04},/*;,27*/ {0x00,0x00,0x00,0x40,0x20,0x10,0x08,0x04,0x02,0x04,0x08,0x10,0x20,0x40,0x00,0x00},/*,28*/ {0x00,0x00,0x00,0x00,0x00,0x00,0x7F,0x00,0x00,0x00,0x7F,0x00,0x00,0x00,0x00,0x00},/*,29*/ {0x00,0x00,0x00,0x02,0x04,0x08,0x10,0x20,0x40,0x20,0x10,0x08,0x04,0x02,0x00,0x00},/*,30*/ {0x00,0x00,0x00,0x3C,0x42,0x42,0x46,0x40,0x20,0x10,0x10,0x00,0x18,0x18,0x00,0x00},/*?,31*/ {0x00,0x00,0x00,0x1C,0x22,0x5A,0x55,0x55,0x55,0x55,0x2D,0x42,0x22,0x1C,0x00,0x00},/*,32*/ {0x00,0x00,0x00,0x08,0x08,0x18,0x14,0x14,0x24,0x3C,0x22,0x42,0x42,0xE7,0x00,0x00},/*A,33*/ {0x00,0x00,0x00,0x1F,0x22,0x22,0x22,0x1E,0x22,0x42,0x42,0x42,0x22,0x1F,0x00,0x00},/*B,34*/ {0x00,0x00,0x00,0x7C,0x42,0x42,0x01,0x01,0x01,0x01,0x01,0x42,0x22,0x1C,0x00,0x00},/*C,35*/ {0x00,0x00,0x00,0x1F,0x22,0x42,0x42,0x42,0x42,0x42,0x42,0x42,0x22,0x1F,0x00,0x00},/*D,36*/ {0x00,0x00,0x00,0x3F,0x42,0x12,0x12,0x1E,0x12,0x12,0x02,0x42,0x42,0x3F,0x00,0x00},/*E,37*/ {0x00,0x00,0x00,0x3F,0x42,0x12,0x12,0x1E,0x12,0x12,0x02,0x02,0x02,0x07,0x00,0x00},/*F,38*/ {0x00,0x00,0x00,0x3C,0x22,0x22,0x01,0x01,0x01,0x71,0x21,0x22,0x22,0x1C,0x00,0x00},/*G,39*/ {0x00,0x00,0x00,0xE7,0x42,0x42,0x42,0x42,0x7E,0x42,0x42,0x42,0x42,0xE7,0x00,0x00},/*H,40*/ {0x00,0x00,0x00,0x3E,0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x3E,0x00,0x00},/*I,41*/ {0x00,0x00,0x00,0x7C,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x11,0x0F},/*J,42*/ {0x00,0x00,0x00,0x77,0x22,0x12,0x0A,0x0E,0x0A,0x12,0x12,0x22,0x22,0x77,0x00,0x00},/*K,43*/ {0x00,0x00,0x00,0x07,0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x42,0x7F,0x00,0x00},/*L,44*/ {0x00,0x00,0x00,0x77,0x36,0x36,0x36,0x36,0x2A,0x2A,0x2A,0x2A,0x2A,0x6B,0x00,0x00},/*M,45*/ {0x00,0x00,0x00,0xE3,0x46,0x46,0x4A,0x4A,0x52,0x52,0x52,0x62,0x62,0x47,0x00,0x00},/*N,46*/ {0x00,0x00,0x00,0x1C,0x22,0x41,0x41,0x41,0x41,0x41,0x41,0x41,0x22,0x1C,0x00,0x00},/*O,47*/ {0x00,0x00,0x00,0x3F,0x42,0x42,0x42,0x42,0x3E,0x02,0x02,0x02,0x02,0x07,0x00,0x00},/*P,48*/ {0x00,0x00,0x00,0x1C,0x22,0x41,0x41,0x41,0x41,0x41,0x4D,0x53,0x32,0x1C,0x60,0x00},/*Q,49*/ {0x00,0x00,0x00,0x3F,0x42,0x42,0x42,0x3E,0x12,0x12,0x22,0x22,0x42,0xC7,0x00,0x00},/*R,50*/ {0x00,0x00,0x00,0x7C,0x42,0x42,0x02,0x04,0x18,0x20,0x40,0x42,0x42,0x3E,0x00,0x00},/*S,51*/ {0x00,0x00,0x00,0x7F,0x49,0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x1C,0x00,0x00},/*T,52*/ {0x00,0x00,0x00,0xE7,0x42,0x42,0x42,0x42,0x42,0x42,0x42,0x42,0x42,0x3C,0x00,0x00},/*U,53*/ {0x00,0x00,0x00,0xE7,0x42,0x42,0x22,0x24,0x24,0x14,0x14,0x18,0x08,0x08,0x00,0x00},/*V,54*/ {0x00,0x00,0x00,0x6B,0x49,0x49,0x49,0x49,0x55,0x55,0x36,0x22,0x22,0x22,0x00,0x00},/*W,55*/ {0x00,0x00,0x00,0xE7,0x42,0x24,0x24,0x18,0x18,0x18,0x24,0x24,0x42,0xE7,0x00,0x00},/*X,56*/ {0x00,0x00,0x00,0x77,0x22,0x22,0x14,0x14,0x08,0x08,0x08,0x08,0x08,0x1C,0x00,0x00},/*Y,57*/ {0x00,0x00,0x00,0x7E,0x21,0x20,0x10,0x10,0x08,0x04,0x04,0x42,0x42,0x3F,0x00,0x00},/*Z,58*/ {0x00,0x78,0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x78,0x00},/*[,59*/ {0x00,0x00,0x02,0x02,0x04,0x04,0x08,0x08,0x08,0x10,0x10,0x20,0x20,0x20,0x40,0x40},/*\,60*/ {0x00,0x1E,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x1E,0x00},/*],61*/ {0x00,0x38,0x44,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*^,62*/ {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xFF},/*_,63*/ {0x00,0x06,0x08,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*,64*/ {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x3C,0x42,0x78,0x44,0x42,0x42,0xFC,0x00,0x00},/*a,65*/ {0x00,0x00,0x00,0x03,0x02,0x02,0x02,0x1A,0x26,0x42,0x42,0x42,0x26,0x1A,0x00,0x00},/*b,66*/ {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x38,0x44,0x02,0x02,0x02,0x44,0x38,0x00,0x00},/*c,67*/ {0x00,0x00,0x00,0x60,0x40,0x40,0x40,0x78,0x44,0x42,0x42,0x42,0x64,0xD8,0x00,0x00},/*d,68*/ {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x3C,0x42,0x7E,0x02,0x02,0x42,0x3C,0x00,0x00},/*e,69*/ {0x00,0x00,0x00,0xF0,0x88,0x08,0x08,0x7E,0x08,0x08,0x08,0x08,0x08,0x3E,0x00,0x00},/*f,70*/ {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x7C,0x22,0x22,0x1C,0x02,0x3C,0x42,0x42,0x3C},/*g,71*/ {0x00,0x00,0x00,0x03,0x02,0x02,0x02,0x3A,0x46,0x42,0x42,0x42,0x42,0xE7,0x00,0x00},/*h,72*/ {0x00,0x00,0x00,0x0C,0x0C,0x00,0x00,0x0E,0x08,0x08,0x08,0x08,0x08,0x3E,0x00,0x00},/*i,73*/ {0x00,0x00,0x00,0x30,0x30,0x00,0x00,0x38,0x20,0x20,0x20,0x20,0x20,0x20,0x22,0x1E},/*j,74*/ {0x00,0x00,0x00,0x03,0x02,0x02,0x02,0x72,0x12,0x0A,0x16,0x12,0x22,0x77,0x00,0x00},/*k,75*/ {0x00,0x00,0x00,0x0E,0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x3E,0x00,0x00},/*l,76*/ {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x7F,0x92,0x92,0x92,0x92,0x92,0xB7,0x00,0x00},/*m,77*/ {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x3B,0x46,0x42,0x42,0x42,0x42,0xE7,0x00,0x00},/*n,78*/ {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x3C,0x42,0x42,0x42,0x42,0x42,0x3C,0x00,0x00},/*o,79*/ {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x1B,0x26,0x42,0x42,0x42,0x22,0x1E,0x02,0x07},/*p,80*/ {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x78,0x44,0x42,0x42,0x42,0x44,0x78,0x40,0xE0},/*q,81*/ {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x77,0x4C,0x04,0x04,0x04,0x04,0x1F,0x00,0x00},/*r,82*/ {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x7C,0x42,0x02,0x3C,0x40,0x42,0x3E,0x00,0x00},/*s,83*/ {0x00,0x00,0x00,0x00,0x00,0x08,0x08,0x3E,0x08,0x08,0x08,0x08,0x08,0x30,0x00,0x00},/*t,84*/ {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x63,0x42,0x42,0x42,0x42,0x62,0xDC,0x00,0x00},/*u,85*/ {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xE7,0x42,0x24,0x24,0x14,0x08,0x08,0x00,0x00},/*v,86*/ {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xEB,0x49,0x49,0x55,0x55,0x22,0x22,0x00,0x00},/*w,87*/ {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x76,0x24,0x18,0x18,0x18,0x24,0x6E,0x00,0x00},/*x,88*/ {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xE7,0x42,0x24,0x24,0x14,0x18,0x08,0x08,0x07},/*y,89*/ {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x7E,0x22,0x10,0x08,0x08,0x44,0x7E,0x00,0x00},/*z,90*/ {0x00,0xC0,0x20,0x20,0x20,0x20,0x20,0x10,0x20,0x20,0x20,0x20,0x20,0x20,0xC0,0x00},/*{,91*/ {0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10},/*|,92*/ {0x00,0x06,0x08,0x08,0x08,0x08,0x08,0x10,0x08,0x08,0x08,0x08,0x08,0x08,0x06,0x00},/*},93*/ {0x0C,0x32,0xC2,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*~,94*/ };#endif link.lds SECTIONS {. 0x23E00000;.text : {start.o* (.text)}.data : {* (.data)}.bss : {* (.bss)}} Makefile CC arm-linux-gcc LD arm-linux-ld OBJCOPY arm-linux-objcopy OBJDUMP arm-linux-objdumpINCDIR : $(shell pwd)#预处理器的flagflag就是编译器可选的选项 CPPFLAGS : -nostdlib -nostdinc -I$(INCDIR)/include #C编译器的flag CFLAGS : -Wall -O2 -fno-builtinexport CC LD OBJCOPY OBJDUMP CPPFLAGS CFLAGSobjs : start.o main.o lcd.o led.bin:$(objs)$(LD) -Tlink.lds -o sd2.elf $^$(OBJCOPY) -O binary sd2.elf sd2.bin$(OBJDUMP) -D sd2.elf sd2.dis%.o:%.S$(CC) $(CPPFLAGS) $(CFLAGS) -o $ $ -c%.o:%.c$(CC) $(CPPFLAGS) $(CFLAGS) -o $ $ -cclean:rm *.o *.elf *.bin *.dis mkv210 -f 文件示例:

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