目录
- Archlab
- Part A Y86-64程序
- Part B
iaddq的实现 - Part C 咕咕咕
Archlab
Part A Y86-64程序
规则：给定你一段C语言代码，需要使用\(Y86-64\)汇编代码写出与其函数上等价的代码
由于\(Y86-64\)功能有限，你需要将测试的输入也写在代码中
目录下使用 ./yas test.ys 编译 ./yis test.yo得到运行的结果
要求对于一个链表进行元素求和，其中C代码如下
/* $begin examples */
/* linked list element */
typedef struct ELE {long val;struct ELE *next;
} *list_ptr;/* sum_list - Sum the elements of a linked list */
long sum_list(list_ptr ls)
{long val = 0;while (ls) {val += ls->val;ls = ls->next;}return val;
}/* rsum_list - Recursive version of sum_list */
long rsum_list(list_ptr ls)
{if (!ls)return 0;else {long val = ls->val;long rest = rsum_list(ls->next);return val + rest;}
}
比较简单，直接实现即可
#initialization.pos 0
irmovq stack, %rsp
call main
halt#sample linked list.align 8
ele1:.quad 0x00a.quad ele2
ele2:.quad 0x0b0.quad ele3
ele3:.quad 0xc00.quad 0#main functionmain:irmovq ele1, %rdicall sum_listret#sum_list functionsum_list:irmovq $0, %raxjmp testloop:mrmovq (%rdi), %rsiaddq %rsi, %raxmrmovq 8(%rdi), %rditest:andq %rdi, %rdijne loopret#set initial adress of %rsp.pos 0x200
stack:最后需要多打一个换行才能过编译，我也不知道为什么（
#initialization.pos 0
irmovq stack, %rsp
call main
halt#sample linked list.align 8
ele1:.quad 0x00a.quad ele2
ele2:.quad 0x0b0.quad ele3
ele3:.quad 0xc00.quad 0#main function
main:irmovq ele1, %rdiirmovq $0, %raxcall rsum_listret#recursively calculate the sum of a listrsum_list:pushq %rbpandq %rdi, %rdije returnmrmovq (%rdi), %rbpaddq %rbp, %raxmrmovq 8(%rdi), %rdicall rsum_list
return:popq %rbpret#set initial adress of %rsp.pos 0x200
stack:注意递归结束的时候，需要恢复被调用者保存寄存器的原始值
/* copy_block - Copy src to dest and return xor checksum of src */
long copy_block(long *src, long *dest, long len)
{long result = 0;while (len > 0) {long val = *src++;*dest++ = val;result ^= val;len--;}return result;
}
/* $end examples */
#initialization.pos 0
irmovq stack, %rsp
call main
halt#sample.align 8
# Source block
src:.quad 0x00a.quad 0x0b0.quad 0xc00
# Destination block
dest:.quad 0x111.quad 0x222.quad 0x333#main functionmain:irmovq src, %rdiirmovq dest, %rsiirmovq $3, %rdxirmovq $0, %raxirmovq $8, %rcxirmovq $1, %r8call copy_blockret#copy functioncopy_block:pushq %rbx
test:andq %rdx, %rdxje return
loop:mrmovq (%rdi), %rbxxorq %rbx, %raxrmmovq %rbx, (%rsi)addq %rcx, %rdiaddq %rcx, %rsisubq %r8, %rdxjmp test
return:popq %rbxret.pos 0x200
stack:Part B iaddq的实现
给定你SEQ的实现，要求你补充iaddq指令(即将寄存器加上一个立即数)的实现
按照SEQ的步骤，一步一步判断每个相关信号的值就行
#/* $begin seq-all-hcl */
####################################################################
# HCL Description of Control for Single Cycle Y86-64 Processor SEQ #
# Copyright (C) Randal E. Bryant, David R. O'Hallaron, 2010 #
###################################################################### Your task is to implement the iaddq instruction
## The file contains a declaration of the icodes
## for iaddq (IIADDQ)
## Your job is to add the rest of the logic to make it work####################################################################
# C Include's. Don't alter these #
####################################################################quote '#include <stdio.h>'
quote '#include "isa.h"'
quote '#include "sim.h"'
quote 'int sim_main(int argc, char *argv[]);'
quote 'word_t gen_pc(){return 0;}'
quote 'int main(int argc, char *argv[])'
quote ' {plusmode=0;return sim_main(argc,argv);}'####################################################################
# Declarations. Do not change/remove/delete any of these #
######################################################################### Symbolic representation of Y86-64 Instruction Codes #############
wordsig INOP 'I_NOP'
wordsig IHALT 'I_HALT'
wordsig IRRMOVQ 'I_RRMOVQ'
wordsig IIRMOVQ 'I_IRMOVQ'
wordsig IRMMOVQ 'I_RMMOVQ'
wordsig IMRMOVQ 'I_MRMOVQ'
wordsig IOPQ 'I_ALU'
wordsig IJXX 'I_JMP'
wordsig ICALL 'I_CALL'
wordsig IRET 'I_RET'
wordsig IPUSHQ 'I_PUSHQ'
wordsig IPOPQ 'I_POPQ'
# Instruction code for iaddq instruction
wordsig IIADDQ 'I_IADDQ'##### Symbolic represenations of Y86-64 function codes #####
wordsig FNONE 'F_NONE' # Default function code##### Symbolic representation of Y86-64 Registers referenced explicitly #####
wordsig RRSP 'REG_RSP' # Stack Pointer
wordsig RNONE 'REG_NONE' # Special value indicating "no register"##### ALU Functions referenced explicitly #####
wordsig ALUADD 'A_ADD' # ALU should add its arguments##### Possible instruction status values #####
wordsig SAOK 'STAT_AOK' # Normal execution
wordsig SADR 'STAT_ADR' # Invalid memory address
wordsig SINS 'STAT_INS' # Invalid instruction
wordsig SHLT 'STAT_HLT' # Halt instruction encountered##### Signals that can be referenced by control logic ######################### Fetch stage inputs #####
wordsig pc 'pc' # Program counter
##### Fetch stage computations #####
wordsig imem_icode 'imem_icode' # icode field from instruction memory
wordsig imem_ifun 'imem_ifun' # ifun field from instruction memory
wordsig icode 'icode' # Instruction control code
wordsig ifun 'ifun' # Instruction function
wordsig rA 'ra' # rA field from instruction
wordsig rB 'rb' # rB field from instruction
wordsig valC 'valc' # Constant from instruction
wordsig valP 'valp' # Address of following instruction
boolsig imem_error 'imem_error' # Error signal from instruction memory
boolsig instr_valid 'instr_valid' # Is fetched instruction valid?##### Decode stage computations #####
wordsig valA 'vala' # Value from register A port
wordsig valB 'valb' # Value from register B port##### Execute stage computations #####
wordsig valE 'vale' # Value computed by ALU
boolsig Cnd 'cond' # Branch test##### Memory stage computations #####
wordsig valM 'valm' # Value read from memory
boolsig dmem_error 'dmem_error' # Error signal from data memory####################################################################
# Control Signal Definitions. #
#################################################################################### Fetch Stage #################################### Determine instruction code
word icode = [imem_error: INOP;1: imem_icode; # Default: get from instruction memory
];# Determine instruction function
word ifun = [imem_error: FNONE;1: imem_ifun; # Default: get from instruction memory
];bool instr_valid = icode in { INOP, IHALT, IRRMOVQ, IIRMOVQ, IRMMOVQ, IMRMOVQ,IOPQ, IJXX, ICALL, IRET, IPUSHQ, IPOPQ, IIADDQ};# Does fetched instruction require a regid byte?
bool need_regids =icode in { IRRMOVQ, IOPQ, IPUSHQ, IPOPQ, IIRMOVQ, IRMMOVQ, IMRMOVQ , IIADDQ};# Does fetched instruction require a constant word?
bool need_valC =icode in { IIRMOVQ, IRMMOVQ, IMRMOVQ, IJXX, ICALL , IIADDQ};################ Decode Stage ##################################### What register should be used as the A source?
word srcA = [icode in { IRRMOVQ, IRMMOVQ, IOPQ, IPUSHQ } : rA;icode in { IPOPQ, IRET } : RRSP;1 : RNONE; # Don't need register
];## What register should be used as the B source?
word srcB = [icode in { IOPQ, IRMMOVQ, IMRMOVQ, IIADDQ } : rB;icode in { IPUSHQ, IPOPQ, ICALL, IRET } : RRSP;1 : RNONE; # Don't need register
];## What register should be used as the E destination?
word dstE = [icode in { IRRMOVQ } && Cnd : rB;icode in { IIRMOVQ, IOPQ, IIADDQ} : rB;icode in { IPUSHQ, IPOPQ, ICALL, IRET } : RRSP;1 : RNONE; # Don't write any register
];## What register should be used as the M destination?
word dstM = [icode in { IMRMOVQ, IPOPQ } : rA;1 : RNONE; # Don't write any register
];################ Execute Stage ##################################### Select input A to ALU
word aluA = [icode in { IRRMOVQ, IOPQ } : valA;icode in { IIRMOVQ, IRMMOVQ, IMRMOVQ , IIADDQ} : valC;icode in { ICALL, IPUSHQ } : -8;icode in { IRET, IPOPQ } : 8;# Other instructions don't need ALU
];## Select input B to ALU
word aluB = [icode in { IRMMOVQ, IMRMOVQ, IOPQ, ICALL, IPUSHQ, IRET, IPOPQ , IIADDQ} : valB;icode in { IRRMOVQ, IIRMOVQ } : 0;# Other instructions don't need ALU
];## Set the ALU function
word alufun = [icode == IOPQ : ifun;1 : ALUADD;
];## Should the condition codes be updated?
bool set_cc = icode in { IOPQ , IIADDQ};################ Memory Stage ##################################### Set read control signal
bool mem_read = icode in { IMRMOVQ, IPOPQ, IRET };## Set write control signal
bool mem_write = icode in { IRMMOVQ, IPUSHQ, ICALL };## Select memory address
word mem_addr = [icode in { IRMMOVQ, IPUSHQ, ICALL, IMRMOVQ } : valE;icode in { IPOPQ, IRET } : valA;# Other instructions don't need address
];## Select memory input data
word mem_data = [# Value from registericode in { IRMMOVQ, IPUSHQ } : valA;# Return PCicode == ICALL : valP;# Default: Don't write anything
];## Determine instruction status
word Stat = [imem_error || dmem_error : SADR;!instr_valid: SINS;icode == IHALT : SHLT;1 : SAOK;
];################ Program Counter Update ############################## What address should instruction be fetched atword new_pc = [# Call. Use instruction constanticode == ICALL : valC;# Taken branch. Use instruction constanticode == IJXX && Cnd : valC;# Completion of RET instruction. Use value from stackicode == IRET : valM;# Default: Use incremented PC1 : valP;
];
#/* $end seq-all-hcl */
