pre_cts_opt

####################################################################################
set design_name             [dbGet top.name]
set pre_stage               pre_place
set post_stage              pre_cts_opt
set process                 180 
set init_design_uniquify 1set VER_NAME [exec /bin/date +%m%d_%H%M]
if {[info exists env(NETLIST_VER)]} { set NETLIST_VER $env(NETLIST_VER) }# unplaceAllGuides
#source ./scr/user_derate
#################################################################################
##sizeonly
dbset [get_property [get_cells [exec cat ../../../syn/output/$NETLIST_VER/set_size_only.txt]] dbObject].dontTouch sizeOK#################################################################################
##dontuse
set_dont_use  DFFHQX1
set_dont_use  DFFHQXL
set_dont_use  DFFNXL
set_dont_use  DFFRHQX1
set_dont_use  DFFRHQX2
set_dont_use  DFFRHQX4
set_dont_use  DFFRHQXL
set_dont_use  DFFRX2
set_dont_use  DFFSX1
set_dont_use  DFFTRXL
set_dont_use  DFFX1
set_dont_use  DFFXL
set_dont_use  EDFFX1
set_dont_use  SDFFHQX1
set_dont_use  SDFFHQX2
set_dont_use  SDFFHQXL
set_dont_use  SDFFSRX2
set_dont_use  SDFFTRX1
set_dont_use  SDFFTRXL
set_dont_use  SDFFX1
set_dont_use  SDFFXL
set_dont_use  SDFFXL
set_dont_use  SEDFFTRXL
set_dont_use  SEDFFXL
#################################################################################
##### Reset all mode
setDesignMode     -reset
setPlaceMode      -reset
setOptMode        -reset
setUsefulSkewMode -reset
setCTSMode        -reset
setTrialRouteMode -reset
setNanoRouteMode  -reset
setExtractRCMode  -reset
setAnalysisMode   -reset
setDelayCalMode   -reset
setSIMode         -reset
setIlmMode        -reset#################################################################################
##### Enable multi-cpu
setMultiCpuUsage -localCpu 16
#################################################################################
##### Design mode (extreme , standard)
setDesignMode -process $process
setDesignMode -flowEffort standard
setDesignMode -highSpeedCore truesetNanoRouteMode -quiet routeWithViaInPin false
setNanoRouteMode -quiet drouteViaOnGridOnly false
setNanoRouteMode -quiet envAlignNonPreferredTrack true
setNanoRouteMode -drouteEndIteration 15
setNanoRouteMode -droutePostRouteSwapViaPriority false
setPlaceMode -place_detail_check_route true
#################################################################################
##### Global setting
set_global timing_report_launch_clock_path true
set_global timing_clock_phase_propagation both
set_global timing_use_incremental_si_transition trueset_table_style -no_frame_fix_width
set_global timing_report_enable_auto_column_width true
set_global report_timing_format {instance cell arc delay arrival incr_delay slew load fanout adjustment}clearGlobalNets 
globalNetConnect VCC1V8 -type pgpin -pin VDD -all -override -verbose -netlistOverride
globalNetConnect GND -type pgpin -pin VSS -all -override -verbose -netlistOverride
globalNetConnect VCC3V3 -type pgpin -pin VDD33 -all -override -verbose -netlistOverride#################################################################################
setTrialRouteMode -minRouteLayer 2
setTrialRouteMode -maxRouteLayer 4
#setRouteMode -earlyGlobalMaxRouteLayer 2
#setRouteMode -earlyGlobalMinRouteLayer 6
setNanoRouteMode -routeBottomRoutingLayer 2
setNanoRouteMode -routeTopRoutingLayer 4
#setDesignMode -bottomRoutingLayer 2
#setDesignMode -topRoutingLayer 6#################################################################################
## placement setting
setPlaceMode -coreEngineEffort high
setPlaceMode -congEffort high
setPlaceMode -maxDensity 0.80
##setPlaceMode -place_detail_preroute_as_obs {2 4}
#
setPlaceMode -place_detail_check_route true
#################################################################################
setOptMode -effort high
setOptMode -fixFanoutLoad true
setOptMode -reclaimArea true
setOptMode -allEndPoints true
setOptMode -maxDensity 0.80 -maxLocalDensity 0.75
setOptMode -maxLength 600setOptMode -usefulSkew false
setOptMode -usefulSkewPreCTS false# setOptMode -powerEffort high#################################################################################
##### STA setting
setDelayCalMode -engine aae -SIAware false
#setDelayCalMode -equivalent_waveform_model_propagation true
#setDelayCalMode -equivalent_waveform_model_type ecsmsetAnalysisMode -cppr both -analysisType onChipVariation
setAnalysisMode -honorClockDomains false#################################################################################
##### dont use setting
#set cell_list "MOAI1S BUF1S"
#
#foreach cell $cell_list {#setDontUse  $cell true
#}
#
#################################################################################
##### update constraints
set_interactive_constraint_modes [all_constraint_modes -active]
#set_ideal_network [get_object_name [add_to_collection -unique "" [get_property [get_clocks -filter "defined(sources)"] sources]]]
set_ideal_network [get_property [all_clocks] sources]
set_clock_uncertainty 0.4 -setup [all_clocks]
set_clock_uncertainty 0.4 -hold [all_clocks]
set_max_transition 0.8 [current_design]
set_max_capacitance 0.3  [current_design]
setOptMode -maxlength  600 
set_max_fanout 32 [current_design ]
set_interactive_constraint_modes " "
#################################################################################
#set_interactive_constraint_modes ""
##### custom path group
set_dont_use "CLKINVX1 CLKINVX2 CLKINVX3 CLKINVX12 CLKINVX16 CLKINVX20 CLKBUFX1 CLKBUFX2 CLKBUFX3 CLKBUFX12 CLKBUFX16 CLKBUFX20"
reset_path_group
resetPathGroupOptions
# createBasicPathGroups -expandedcreateBasicPathGroups -expanded#setPlaceMode -place_global_place_io_pins true
##################################################################################
#setPlaceMode -placeIsetOptMode -addPortpre_cts_opt.tclAsNeeded falseOPins 1#setOptMode -addPortAsNeeded false#timeDesign -preplace -expandedViews -outDir  ./report/${pre_stage}  -prefix ${pre_stage} -numPaths 500
place_opt_design                    -out_dir ./report/place         -prefix place
#timeDesign -preCTS -expandedViews   -outDir  ./report/${post_stage} -prefix ${post_stage} -numPaths 500#setFillerMode -corePrefix FILLER -core "FDCAPHD4 FDCAPHD8 F_FILLHD1 F_FILLHD2 F_FILLHD4 F_FILLHD8 F_FILLHD16"
#addFiller
#scanReorder -scanEffort high
#setTieHiLoMode -maxFanout 1 -maxDistance 20
#addTieHiLo -cell "JLSCL6CNMV2_CONB_0" -prefix TIE#optDesign -preCts -incr -outDir reports/${post_stage} -prefix ${post_stage}_incr
#saveDesign -tcon -verilog DBS/${post_stage}_incr_${VER_NAME}.enc
#timeDesign -preCTS -expandedViews -outDir reports/${post_stage} -prefix ${post_stage}_incr -numPaths 500#################################################################################
##### save result#remove_assigns ; deleteEmptyModule
saveDesign -tcon  ../DB/${design_name}_${NETLIST_VER}_${post_stage}_${VER_NAME}.enc
#defOut -scanChain -netlist -floorplan -placement -routing DBS/${post_stage}_${VER_NAME}.def.gz
#timeDesign -preCTS -expandedViews -outDir reports/${post_stage} -prefix ${post_stage} -numPaths 500
timeDesign -preCTS -expandedViews -outDir reports/${post_stage} -prefix ${post_stage} -numPaths 500