ccopt

#################################################################################
##### common setting
set design_name             [dbGet top.name]
set pre_stage               pre_cts_opt
set post_stage              ccopt
set process                 180 
set VER_NAME [exec /bin/date +%m%d_%H%M]
if {[info exists env(NETLIST_VER)]} { set NETLIST_VER $env(NETLIST_VER) }##################################################################################
### RESET MODE
#setDesignMode     -reset
#setPlaceMode      -reset
#setOptMode        -reset
#setUsefulSkewMode -reset
#setCTSMode        -reset
#setTrialRouteMode -reset
#setNanoRouteMode  -reset
#setExtractRCMode  -reset
#setAnalysisMode   -reset
#setDelayCalMode   -reset
#setSIMode         -reset
#setIlmMode        -reset
#
##################################################################################
### GLOBAL MODE SET
set_global timing_report_launch_clock_path true
set_global timing_clock_phase_propagation both
set_global timing_use_incremental_si_transition true
#
#set_table_style -no_frame_fix_width
#set_global timing_report_enable_auto_column_width true
set_global report_timing_format {instance cell arc delay arrival incr_delay slew load fanout user_derate adjustment}
#
#
### define cpu and process
#setMultiCpuUsage -localCpu 8
#
##################################################################################
### Design mode (extreme , high)
#setDesignMode -process 150
#setDesignMode -flowEffort standard
#setDesignMode -highSpeedCore true
#
##################################################################################
##setTrialRouteMode -minRouteLayer 2
##setTrialRouteMode -maxRouteLayer 6
##setRouteMode -earlyGlobalMaxRouteLayer 6
##setRouteMode -earlyGlobalMinRouteLayer 2
#
##################################################################################
### placement setting
#setPlaceMode -coreEngineEffort high
#setPlaceMode -congEffort high
#setPlaceMode -maxDensity 0.80
#
##################################################################################
### opt mode
setOptMode -allEndPoints true
setOptMode -reclaimArea true
setOptMode -reclaimAreaIncremental true
setOptMode -fixFanoutLoad true
#setOptMode -clkGateAware force
setOptMode -maxDensity 0.8
setOptMode -maxLength 600
setOptMode -effort high
#
setOptMode -usefulSkew false
setOptMode -usefulSkewCTS false
setOptMode -usefulSkewPostCTS false
setNanoRouteMode -quiet routeWithViaInPin false
setNanoRouteMode -quiet drouteViaOnGridOnly false
setNanoRouteMode -quiet envAlignNonPreferredTrack true#################################################################################
## nanoroute setting. (drc/ant)
setNanoRouteMode -routeBottomRoutingLayer 2
setNanoRouteMode -routeTopRoutingLayer 4 
setNanoRouteMode -routeWithTimingDriven true
setNanoRouteMode -routeWithSiDriven true
setNanoRouteMode -routeWithSiPostRouteFix true
setNanoRouteMode -routeSiEffort high#################################################################################
## CTS mode
setCTSMode -routeClkNet true
set_ccopt_property -check_route_follows_guide  true
#setCTSMode -routeGuide true
##setCTSMode -routeTopPreferredLayer 4 
#setCTSMode -routeBottomPreferredLayer 2
#setCTSMode -routePreferredExtraSpace 0
#setCTSMode -routeLeafTopPreferredLayer 4
#setCTSMode -routeLeafBottomPreferredLayer 2
#setCTSMode -routeLeafPreferredExtraSpace 1#################################################################################
##### STA mode
setAnalysisMode -cppr both -analysisType onChipVariation
setDelayCalMode -engine aae -SIAware false#################################################################################
##### Dont use setting
#set cell_list ""
#foreach cell $cell_list {
#  setDontUse  $cell true
#}
#setDontUse *BWP35LVT false
#setDontUse *CD3NMLVT false#################################################################################
##### update constraints
set_interactive_constraint_modes [all_constraint_modes -active]reset_ideal_network [get_property [all_clocks] sources]
reset_ideal_latency [get_property [all_clocks] sources]set_max_transition 0.8 [current_design]
set_max_transition 0.4 -clock_path [all_clocks]
set_max_capacitance 0.3 [current_design ]
set_max_transition 0.4 [all_clocks]
#set_clock_uncertainty 0.4 -setup [all_clocks]
#set_clock_uncertainty 0.4 -hold [all_clocks]set_interactive_constraint_modes ""
setOptMode -maxLength 600#set_propagated_clock [all_clocks]
##reset_ideal_network [get_object_name [add_to_collection -unique "" [get_property [get_clocks -filter "defined(sources)"] sources]]]
#set_propagated_clock [get_ports rst]
##set_ccopt_property target_max_capacitance 0.3 [current_design]
##set_ccopt_property max_fanout 32 [current_design ]
##
##set_ccopt_property target_max_trans 0.8 [current_design]
##set_ccopt_property target_max_trans 0.4 [all_clocks]
##set_clock_uncertainty 0.4 -setup [all_clocks]
##set_clock_uncertainty 0.4 -hold [all_clocks]
##set_interactive_constraint_modes ""
##setOptMode -maxLength 600#################################################################################
##### custom path group
reset_path_group
resetPathGroupOptions
createBasicPathGroups -expanded
#set allreg [all_registers]
#group_path -name reg2reg -from [all_registers] -to [all_registers]
#group_path -name reg2icg -from [all_registers] -to [get_cells -hier -filter "is_integrated_clock_gating_cell==true"]
#group_path -name reg2asy -from [all_registers] -to [all_registers -async_pins]
#group_path -name reg2out -from [all_registers] -to [all_outputs]
#group_path -name in2reg  -from [all_inputs]    -to [all_registers]
#group_path -name in2out  -from [all_inputs]    -to [all_outputs]
#group_path -name reg2mem -from [all_registers] -to u_digi_top/u_platform/u_ahb_top_0/usram8kb/usram8kb/usram2048x32
#group_path -name mem2reg -from u_digi_top/u_platform/u_ahb_top_0/usram8kb/usram8kb/usram2048x32 -to [all_registers]
#group_path -name reg2ana -from [all_registers] -to u_ana_top
#group_path -name ana2reg -from u_ana_top -to [all_registers]
#group_path -name reg2lcd -from [all_registers] -to u_ana_lcdsw
#group_path -name lcd2reg -from u_ana_lcdsw -to [all_registers]
#
#setPathGroupOptions reg2reg -effortLevel high -late -slackAdjustment 0.0
#setPathGroupOptions reg2icg -effortLevel high -late -slackAdjustment 0.0
#setPathGroupOptions reg2asy -effortLevel high -late -slackAdjustment 0.0
#setPathGroupOptions reg2out -effortLevel low  -late -slackAdjustment 0.0
#setPathGroupOptions in2reg  -effortLevel low  -late -slackAdjustment 0.0
#setPathGroupOptions in2out  -effortLevel low  -late -slackAdjustment 0.0
#setPathGroupOptions default -effortLevel high -late -slackAdjustment 0.0
#
#setPathGroupOptions reg2mem -effortLevel high -late -slackAdjustment 0.0
#setPathGroupOptions mem2reg -effortLevel high -late -slackAdjustment 0.0
#
#setPathGroupOptions reg2ana -effortLevel low  -late -slackAdjustment 0.0
#setPathGroupOptions ana2reg -effortLevel low  -late -slackAdjustment 0.0
#setPathGroupOptions reg2lcd -effortLevel low  -late -slackAdjustment 0.0
#setPathGroupOptions lcd2reg -effortLevel low  -late -slackAdjustment 0.0
#
#reportPathGroupOptions
#
# 
#setFillerMode -core {JLSCL6CNMV2_DECAP_16 JLSCL6CNMV2_DECAP_8 JLSCL6CNMV2_DECAP_6 JLSCL6CNMV2_DECAP_4 JLSCL6CNMV2_DECAP_3 JLSCL6CNMV2_FILL_32 JLSCL6CNMV2_FILL_16 JLSCL6CNMV2_FILL_8 JLSCL6CNMV2_FILL_4 JLSCL6CNMV2_FILL_3 JLSCL6CNMV2_FILL_2 JLSCL6CNMV2_FILL_1} -corePrefix FILLER#################################################################################
# create_ccopt_clock_tree_spec -file  DBS/CTS/ccopt_${VER_NAME}.spec -keep_all_sdc_clocks
#create_clock [get_ports rst]  -name rst_clk  -period 1000
#create_ccopt_clock_tree_spec
set_ccopt_mode -cts_inverter_cells "CLKINVX8 CLKINVX3 CLKINVX4 CLKINVX12"
set_ccopt_mode -cts_target_slew 0.7
set_ccopt_mode -cts_target_nonleaf_slew 0.7
set_ccopt_mode -cts_target_skew 0.3
set_ccopt_mode -cts_inverter_cells true
set_ccopt_property max_fanout 32#setFillerMode -corePrefix FILLER -core "FDCAPHD4 FDCAPHD8 F_FILLHD1 F_FILLHD2 F_FILLHD4 F_FILLHD8 F_FILLHD16"
#set_dont_use "INV1CK BUF"
set_dont_use "CLKINVX1 CLKINVX2  CLKINVX16 CLKINVX20 CLKBUFX1 CLKBUFX2 CLKBUFX3 CLKBUFX12 CLKBUFX16 CLKBUFX20 " truedelete_ccopt_clock_trees *
#delete_ccopt_skew_groups *
create_ccopt_clock_tree_spec -file ccopt_spec.spec
source ./ccopt_spec.spec
##source ./scr/inseration.tcl
#source /home/cdsuser1/Project/zx5017/APR/tmp/scr/inseration.tcl#################################################################################
##add_ndr
add_ndr -name 2w2s -width {METAL2:METAL4 0.56} -spacing {METAL2:METAL4 0.56}create_route_type -name top_rule \-preferred_routing_layer_effort high \-top_preferred_layer 4 \-bottom_preferred_layer 2 \-shield_net GND \-shield_side both_side \-non_default_rule 2w2s
create_route_type -name trunk_rule \-preferred_routing_layer_effort high \-top_preferred_layer 4 \-bottom_preferred_layer 2 \-shield_net GND \-shield_side both_side \-non_default_rule 2w2s
create_route_type -name leaf_rule \-top_preferred_layer 4 \-bottom_preferred_layer 2 \-shield_net GND \-shield_side both_side \-non_default_rule 2w2s
set_ccopt_property route_type -net_type top top_rule                                  
set_ccopt_property route_type -net_type trunk trunk_rule
set_ccopt_property route_type -net_type leaf leaf_ruleadd_ndr -name 1w1s -width {METAL2:METAL4 0.28} -spacing {METAL2:METAL4 0.28}create_route_type -name top_rule_1 \-preferred_routing_layer_effort high \-top_preferred_layer 4 \-bottom_preferred_layer 2 \-shield_net GND \-shield_side both_side \-non_default_rule 1w1s
create_route_type -name trunk_rule_1 \-preferred_routing_layer_effort high \-top_preferred_layer 4 \-bottom_preferred_layer 2 \-shield_net GND \-shield_side both_side \-non_default_rule 1w1s
create_route_type -name leaf_rule_1 \-top_preferred_layer 4 \-bottom_preferred_layer 2 \-shield_net GND \-shield_side both_side \-non_default_rule 1w1s
set_ccopt_property route_type -net_type top top_rule_1                                  
set_ccopt_property route_type -net_type trunk trunk_rule_1
set_ccopt_property route_type -net_type leaf leaf_rule_1ccopt_design -outDir ./report/ccopt -prefix ccopttimeDesign -postCTS 
timeDesign -postCTS -hold 
#optDesign -postCTS -incr
#optDesign -postCTS -hold #remove_assigns ; deleteEmptyModule
saveDesign -tcon ../DB/${design_name}_${NETLIST_VER}_${post_stage}_${VER_NAME}.enc
##defOut -scanChain -netlist -floorplan -placement -routing DBS/${post_stage}_${VER_NAME}.def.gz
#timeDesign -postCTS -expandedViews       -outDir ./report/${post_stage} -prefix ${post_stage}_${VER_NAME} -numPaths 1000
#timeDesign -postCTS -hold -expandedViews -outDir ./report/${post_stage} -prefix ${post_stage}_${VER_NAME} -numPaths 2000#set del_cell_list [list DELHD0 DELHD1 DELHD2 DELHD3 DELHD4] 
#setOptMode -ignorePathGroupsForHold {in2reg reg2out}
#optDesign -postCTS -hold -outDir ../rpt/${post_stage} -prefix hold
#saveDesign -tcon -verilog ../DB/${design_name}_${post_stage}_hold_${VER_NAME}.enc#####################################################################################
#set del_cell_list [list JLSCL6CNMV2_BUF_1 JLSCL6CNMV2_BUF_2 JLSCL6CNMV2_DLYGATE4S50_1 JLSCL6CNMV2_DLYGATE4S18_1 JLSCL6CNMV2_DLYGATE4S12_1] 
#setOptMode -holdFixingCells $del_cell_list
#setOptMode -verbose true
#optDesign -postCTS -hold -outDir reports/${post_stage} -prefix ${post_stage}_hold
#
#remove_assigns ; deleteEmptyModule
#saveDesign -tcon -verilog DBS/${post_stage}_hold_${VER_NAME}.enc
#
#timeDesign -expandedViews -postCTS -pathreports -drvReports -numPaths 5000 -outDir reports/${post_stage} -prefix ${post_stage}_hold
#timeDesign -expandedViews -postCTS -hold -pathreports -numPaths 5000 -outDir reports/${post_stage} -prefix ${post_stage}_hold
#
#######################################################################################
#optDesign -postCTS -incr -outDir reports/postCTS_incr -prefix postCTS_incr_${VER_NAME}
#
#remove_assigns ; deleteEmptyModule
#saveDesign -tcon -verilog DBS/postCTS_incr_${VER_NAME}.en"%!*
#
#timeDesign -expandedViews -postCTS -pathreports -drvReports -numPaths 500 -outDir reports/${post_stage} -prefix postCTS_incr_${VER_NAME}
#timeDesign -expandedViews -postCTS -hold -pathreports -numPaths 500 -outDir reports/${post_stage} -prefix postCTS_incr_${VER_NAME}#################################################################################
##### Save result#if {[checkUnique] > 0} { deleteEmptyModule }
#saveDesign -tcon -libs -verilog DBS/${post_stage}_${VER_NAME}.enc
#defOut -scanChain -netlist -floorplan -placement -routing DBS/${post_stage}_${VER_NAME}.def.gz