一ADC：

16bit精度+DDR+LVDS+8个outpin

二：FPGA处理流程：

1.差分数据转单端+idelaye2+generate for

generate
for(i=0;i<=7;i=i+1)begin:GEN_IN
IBUFDS #(.DIFF_TERM("TRUE"),       // Differential Termination.IBUF_LOW_PWR("FALSE"),     // Low power="TRUE", Highest performance="FALSE" .IOSTANDARD("LVDS")     // Specify the input I/O standard
) 
u_inbufds(.O(data_in[i]),  // Buffer output.I(din_p[i]),  // Diff_p buffer input (connect directly to top-level port).IB(din_n[i]) // Diff_n buffer input (connect directly to top-level port)
);(* IODELAY_GROUP = "selectio_wiz_0_group" *)
IDELAYE2# (.CINVCTRL_SEL           ("FALSE"),                            // TRUE, FALSE.DELAY_SRC              ("IDATAIN"),                          // IDATAIN, DATAIN.HIGH_PERFORMANCE_MODE  ("FALSE"),                            // TRUE, FALSE.IDELAY_TYPE            ("FIXED"),              // FIXED, VARIABLE, or VAR_LOADABLE.IDELAY_VALUE           (IDELAY_VALUE),                  // 0 to 31.REFCLK_FREQUENCY       (200.0),.PIPE_SEL               ("FALSE"),.SIGNAL_PATTERN         ("DATA"))                             // CLOCK, DATAidelaye2_bus(.DATAOUT                (data_dly[i]),.DATAIN                 (1'b0),                               // Data from FPGA logic.C                      (1'b0),.CE                     (),.INC                    (),.IDATAIN                (data_in[i]), // Driven by IOB.LD                     (1'b0),.REGRST                 (),.LDPIPEEN               (1'b0),.CNTVALUEIN             (5'b00000),.CNTVALUEOUT            (),.CINVCTRL               (1'b0));
end
endgenerate

2.iddr+generate for

generate
for(i=0;i<=7;i=i+1)begin:GEN_IDDR
IDDR #(.DDR_CLK_EDGE("SAME_EDGE_PIPELINED"), // "OPPOSITE_EDGE", "SAME_EDGE" //.DDR_CLK_EDGE("SAME_EDGE"), // "OPPOSITE_EDGE", "SAME_EDGE" //    or "SAME_EDGE_PIPELINED" .INIT_Q1(1'b0), // Initial value of Q1: 1'b0 or 1'b1.INIT_Q2(1'b0), // Initial value of Q2: 1'b0 or 1'b1.SRTYPE("ASYNC") // Set/Reset type: "SYNC" or "ASYNC" ) IDDR_inst (.Q1   (data_in_n0[i]), // 1-bit output for positive edge of clock .Q2   (data_in_n1[i]), // 1-bit output for negative edge of clock.C    (clkin_sys),   // 1-bit clock input.CE   (1'b1), // 1-bit clock enable input.D    (data_dly[i]),   // 1-bit DDR data input.R    (io_reset),   // 1-bit reset.S    (1'b0)    // 1-bit set);
end
endgeneratealways@(posedge clkin_bufr)
begindout_pin <= {  data_in_n1[7],data_in_n0[7],data_in_n1[6],data_in_n0[6],data_in_n1[5],data_in_n0[5],data_in_n1[4],data_in_n0[4],data_in_n1[3],data_in_n0[3],data_in_n1[2],data_in_n0[2],data_in_n1[1],data_in_n0[1],data_in_n1[0],data_in_n0[0]}; 
end