广东官方网站建设,sns社交网站开发教程,wordpress页尾,深圳专业做网站开发费用北邮22信通一枚~ 跟随课程进度更新北邮信通院数字系统设计的笔记、代码和文章 持续关注作者 迎接数电实验学习~ 获取更多文章#xff0c;请访问专栏#xff1a; 北邮22级信通院数电实验_青山如墨雨如画的博客-CSDN博客 先抄作业#xff01;#xff01;#xff01;请访问专栏 北邮22级信通院数电实验_青山如墨雨如画的博客-CSDN博客 先抄作业没时间写解析了等之后慢慢补吧 实验效果参考视频链接 数电第六周实验全加器_哔哩哔哩_bilibili 一.verilog 代码 add.v module add_initial(a,b,ci_1,si,ci);input a,b,ci_1;output si,ci;wire p,g;assign pa^b;assign gab;assign sip^ci_1;assign cig|(pci_1);endmodulemodule my_add(a,b,s,ci,cout);input [3:0] a;input [3:0] b;input ci;output [3:0] s;output cout;wire c1,c2,c3;add_initial u0(.a(a[0]),.b(b[0]),.ci_1(ci),.si(s[0]),.ci(c1));add_initial u1(.a(a[1]),.b(b[1]),.ci_1(c1),.si(s[1]),.ci(c2));add_initial u2(.a(a[2]),.b(b[2]),.ci_1(c2),.si(s[2]),.ci(c3));add_initial u3(.a(a[3]),.b(b[3]),.ci_1(c3),.si(s[3]),.ci(cout)); endmodulemodule add(sw,cal,key_confire_2,key_confire_3,seg_led_1,seg_led_2,clk,rst_n); input clk; input rst_n; input [3:0] sw; input cal; input key_confire_2; input key_confire_3;output reg [8:0] seg_led_1; output reg [8:0] seg_led_2;reg [8:0] seg [15:0]; initial beginseg[0]9h3f;seg[1]9h06;seg[2]9h5b;seg[3]9h4f;seg[4]9h66;seg[5]9h6d;seg[6]9h7d;seg[7]9h07;seg[8]9h7f;seg[9]9h6f;seg[10]9h77;seg[11]9h7c;seg[12]9h39;seg[13]9h5e;seg[14]9h79;seg[15]9h71;endreg [3:0] a; reg [3:0] b; reg iscal;wire [3:0]ans; wire cout; wire ci; always(*)begin if(rst_n0)begina4b0000;b4b0000;iscal0;end if(key_confire_20)begin asw;end if(key_confire_30)begin bsw;end if(cal0)begin iscal1;end endmy_add u(.a(a),.b(b),.s(ans),.ci(ci),.cout(cout)); always(posedge clk) begin if(iscal)beginseg_led_1seg[ans];seg_led_2seg[cout];endelsebegin seg_led_1seg[a];seg_led_2seg[b];end end endmodule 二.管脚分配