LOC
LOC指定逻辑单元对目标SITE资源的放置分配
Xilinx部分。
LOC属性或约束有时与BEL属性一起使用，以定义精确的
将细胞放置在设备内。在这些情况下，必须定义BEL约束
否则将发生放置错误。
提示：要将I/O端口分配给设备包上的物理引脚，请使用package_PIN属性
比LOC。
架构支持
所有架构。
适用对象
•单元（get_cell）
°任何原始细胞
价值观
站点名称（例如，SLICE_X15Y14或RAMB18_X6Y9）
语法
Verilog语法
将Verilog属性放在组件实例化之前。
提示：Verilog属性也可以放在推断寄存器SRL的reg声明之前，或者
当该注册表可以放置在单个设备站点中时，LUTRAM：
(* LOC = "site_name" *)
// Designates placed_reg to be placed in SLICE site SLICE_X0Y0
(* LOC = "SLICE_X0Y0" *) reg placed_reg;
VHDL Syntax
Declare the VHDL attribute as follows:
attribute LOC : string;
For an instantiated instance, specify the VHDL attribute as follows:
attribute LOC of instance_name : label is "site_name";
Where instance_name is the instance name of an instantiated primitive.
VHDL Syntax Example
-- Designates instantiated register instance placed_reg to be placed
-- in SLICE site SLICE_X0Y0
attribute LOC of placed_reg : label is "SLICE_X0Y0";
For an inferred instance, specify the VHDL attribute as follows:
attribute LOC of signal_name : signal is "site_name";
Where
• signal_name is the signal name of an inferred primitive that can be placed into a
single site.
VHDL Syntax Example
-- Designates inferred register placed_reg to be placed in SLICE site SLICE_X0Y0
attribute LOC of placed_reg : signal is "SLICE_X0Y0";
XDC Syntax
set_property LOC site_name [get_cells instance_name]
Where
• instance_name is a primitive instance.
XDC Syntax Example
# Designates placed_reg to be placed in SLICE site SLICE_X0Y0
set_property LOC SLICE_X0Y0 [get_cells placed_reg]
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